公开(公告)号：US20240363453A1

公开(公告)日：2024-10-31

申请号：US18140085

申请日：2023-04-27

申请人： NANYA TECHNOLOGY CORPORATION

发明人： WU-DER YANG

IPC分类号： H01L21/66 ,  G01R31/28 ,  H01L21/78 ,  H01L23/00

CPC分类号： H01L22/32 ,  G01R31/2884 ,  H01L21/78 ,  H01L24/05 ,  H01L2224/05553

摘要： A scribe line structure is provided. The scribe line structure includes a die region, a scribe line region, and one or more circuit probing pads. The die region is disposed on a semiconductor wafer. The scribe line region surrounds the die region. The one or more circuit probing pads are disposed on a first top surface of the die region and a second top surface of the scribe line region.

公开(公告)号：US20240363330A1

公开(公告)日：2024-10-31

申请号：US18308664

申请日：2023-04-27

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Szu Yu HOU

IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/02068 ,  H01L21/31138 ,  H01L21/76814 ,  H01L23/53257

摘要： A semiconductor device includes a substrate and a bit line structure disposed on the substrate. The bit line structure includes a first conductive structure and a second conductive structure, in which a material of the first conductive structure includes polysilicon. The second conductive structure is disposed in direct contact on the first conductive structure, in which a reactivity of a material of the second conductive structure to oxygen is larger than a reactivity of tungsten to oxygen.

公开(公告)号：US12131908B2

公开(公告)日：2024-10-29

申请号：US18383158

申请日：2023-10-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Jar-Ming Ho

IPC分类号： H10B12/00 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532 ,  H01L23/544

CPC分类号： H01L21/28506 ,  H01L21/3213 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/544 ,  H10B12/00 ,  H10B12/09 ,  H10B12/50

摘要： The present disclosure provides a semiconductor structure, which includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a plurality of first conductive plugs penetrating through the dielectric layer; a plurality of spacers surrounding the respective first conductive plugs; a lining layer covering the dielectric layer, the spacer and the first conductive plugs, wherein the lining layer and the first conductive plugs include manganese (Mn); a second conductive plug penetrating through the lining layer; and a second conductive layer over the lining layer and the second conductive plug.

公开(公告)号：US20240347448A1

公开(公告)日：2024-10-17

申请号：US18133061

申请日：2023-04-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： YING-CHENG CHUANG

IPC分类号： H01L23/528 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76877

摘要： The present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate, a residual nitrogen, an oxide layer, a plurality of first contacts, and a plurality of second contacts. The substrate includes a plurality of pillars in an array region of the substrate, wherein a top surface of each of the plurality of pillars is a substantially planar surface. The residual nitrogen is partially disposed on sidewalls of the pillars proximal to the top surfaces of the pillars. The oxide layer surrounds each of the pillars. The plurality of first contacts extends from the top surfaces of the pillars into the pillars. The plurality of second contacts extends from the top surface of the first dielectric layer into the first dielectric layer.

公开(公告)号：US20240347444A1

公开(公告)日：2024-10-17

申请号：US18135319

申请日：2023-04-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： PIN-JHU LI ,  SHIH-FAN KUAN

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76883 ,  H01L28/87 ,  H01L28/91

摘要： A conductive structure and a capacitor structure and a method of manufacturing a conductive structure are provided. The conductive structure includes a first support layer, a second support layer, a first conductive via, a third support layer and a second conductive via. The second support layer is disposed over the first support layer. The first conductive via is disposed between the first support layer and the second support layer. The third support layer is disposed over the second support layer. The second conductive via is disposed between the second support layer and the third support layer, and electrically connected to the first conductive via. A lateral surface of the first conductive via is discontinuous with a lateral surface of the second conductive via.

公开(公告)号：US20240347374A1

公开(公告)日：2024-10-17

申请号：US18135339

申请日：2023-04-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： KUO-CHUNG HSU ,  EN-JUI LI

IPC分类号： H01L21/762 ,  H10B10/00 ,  H10B12/00 ,  H10B20/25

CPC分类号： H01L21/76224 ,  H10B10/18 ,  H10B12/30 ,  H10B20/25

摘要： A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate and a first isolation structure. The substrate has a cell region and a peripheral region. The first isolation structure is disposed in the cell region of the substrate. The first isolation structure includes a first dielectric layer and a second dielectric layer. The second dielectric layer is spaced apart from the substrate by the first dielectric layer. The second dielectric layer is doped with an impurity.

公开(公告)号：US20240345135A1

公开(公告)日：2024-10-17

申请号：US18299711

申请日：2023-04-12

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tien Yu CHEN

IPC分类号： G01R1/44 ,  G01R31/28

CPC分类号： G01R1/44 ,  G01R31/2831

摘要： A preheating control system comprising a testing device and a processor is provided in present disclosure. The testing device is configured to perform a wafer testing on a wafer lot and perform a device preheating on the testing device. The processor is coupled to the testing device and comprises a timing circuit and a controlling circuit. The timing circuit is configured to calculate a lot-changing time, wherein the lot-changing time is a difference between a time corresponding to removal of a previous wafer lot from the testing device and a time corresponding to insertion of the wafer lot into the testing device. The controlling circuit is configured to control the testing device to perform the wafer testing, and configured to control the testing device to perform the device preheating according to the lot-changing time and a standard lot-changing time.

公开(公告)号：US20240339518A1

公开(公告)日：2024-10-10

申请号：US18746358

申请日：2024-06-18

申请人： NANYA TECHNOLOGY CORPORATION

发明人： SHENG-HUI YANG

IPC分类号： H01L29/45 ,  H01L29/40

CPC分类号： H01L29/458 ,  H01L29/401

摘要： A contact structure and a manufacturing method are provided. The contact structure includes a recessed structure, a conductive feature, a first functional layer, a second functional layer and an interfacial layer. The conductive feature is filled in a recess of the recessed structure. The first functional layer extends between the conductive feature and the recessed structure. The second functional layer extends between the first functional layer and the conductive feature. The interfacial extends along an interface between the first and second functional layers, and includes a first element from the first functional layer and a second element from the second functional layer.

公开(公告)号：US20240339398A1

公开(公告)日：2024-10-10

申请号：US18131462

申请日：2023-04-06

申请人： NANYA TECHNOLOGY CORPORATION

发明人： FENG-WEN HSU

IPC分类号： H01L23/528

CPC分类号： H01L23/528

摘要： The present application provides a semiconductor structure having dielectric liner and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate; a first bit line structure, disposed over the substrate, comprising a first conductive layer, a second conductive layer disposed over the first conductive layer, and a first dielectric layer disposed over the second conductive layer; a second bit line structure, disposed over the substrate, comprising a second dielectric layer, a third conductive layer disposed over the second dielectric layer, and a third dielectric layer disposed over the third conductive layer; a polysilicon layer, disposed over the substrate and surrounded by the first bit line structure and the second bit line structure; a dielectric liner, surrounding at least a portion of the polysilicon layer; and a landing pad, disposed over the polysilicon layer, the dielectric liner and the second bit line structure.

公开(公告)号：US12113046B2

公开(公告)日：2024-10-08

申请号：US18386345

申请日：2023-11-02

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Wei-Zhong Li ,  Yi-Ting Shih ,  Chien-Chung Wang ,  Hsih-Yang Chiu

IPC分类号： H01L23/00

CPC分类号： H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/48824 ,  H01L2224/85031 ,  H01L2224/85359

摘要： A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).