Abstract:
An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.
Abstract:
A method of manufacturing a memory device. The memory device comprises a trench in a substrate, a capacitor at the low portion of the trench, a collar dielectric layer overlying the capacitor and covering a portion of the sidewall of the trench, and a conductive layer filling a portion of the trench over the capacitor. First, a first mask layer is formed on the conductive layer, wherein a bottom portion of the first mask layer is thicker than the side portion thereof in the trench. A second mask layer is formed on the first mask layer. Next, a portion of the second mask layer in the trench is ion implanted. The unimplanted portion of the second mask layer is removed.
Abstract:
A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar dielectric layer is lower than top surface level of the filling electrode layer. A vertical transistor is disposed at the upper portion of the trench, comprising a doped region disposed in a portion of the trench adjacent to the trench. A buried conductive layer interposed between the vertical transistor and the trench capacitor, wherein the cross section of the buried conductive layer is H shaped. The trench capacitor and the doping region of vertical transistor are electrically connected through the H shaped buried conductive layer.
Abstract:
Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated the substrate by a collar dielectric layer. A trench top oxide (TTO) layer is disposed on the first conductive layer. A vertical transistor is disposed over the TTO layer. The vertical transistor comprises a gate dielectric layer disposed on the sidewalls of the upper portion of the trench, and a metal gate disposed in the upper portion of the trench.
Abstract:
A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar dielectric layer is lower than top surface level of the filling electrode layer. A vertical transistor is disposed at the upper portion of the trench, comprising a doped region disposed in a portion of the trench adjacent to the trench. A buried conductive layer interposed between the vertical transistor and the trench capacitor, wherein the cross section of the buried conductive layer is H shaped. The trench capacitor and the doping region of vertical transistor are electrically connected through the H shaped buried conductive layer.
Abstract:
A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided, a capacitor wire is formed on the bottom portion of the trench, and a collar dielectric layer is formed between the capacitor wire and the semiconductor substrate to act as an isolation. The capacitor wire and the collar dielectric layer are etched to a predetermined depth, such that a gap is formed between the spacer and the capacitor wire and the collar dielectric layer. Ions are doped into the exposed semiconductor substrate to form an ion doped area acting as a buried strap. The spacer is removed, and an exposed collar dielectric layer is etched below the level of the surface of the capacitor wire, and a groove is formed between the capacitor wire and the trench sidewall to fill with a conducting layer.
Abstract:
A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided, a capacitor wire is formed on the bottom portion of the trench, and a collar dielectric layer is formed between the capacitor wire and the semiconductor substrate to act as an isolation. The capacitor wire and the collar dielectric layer are etched to a predetermined dept, such that a gap is formed between the spacer and the capacitor wire and the collar dielectric layer. Ions are doped into the exposed semiconductor substrate to form an ion doped area acting as a buried strap. The spacer is removed, and an exposed collar dielectric layer is etched below the level of the surface of the capacitor wire, and a groove is formed between the capacitor wire and the trench sidewall to fill with a conducting layer.
Abstract:
The present invention provides a process for planarizing array top oxide (ATO) in vertical MOSFET DRAM arrays. In contrast to the prior art ARC-RIE planarization method for EA/ES (etch array/etch support) module, the present invention takes advantage of chemical mechanical polishing (CMP) technique to overcome residue problems that used to occur at the transition region or array edge. It might cause capacitor device failure when ATO residue is left on the transition region.
Abstract:
A covering device for detachably shielding an access hole which is provided on the top portion of a conduit box, includes a fixing member having a peripheral wall defining a top opening and a bottom opening and a base protruding inwardly therefrom; a plurality of bolts being fixed on the base of the fixing member; a plurality of supporting members respectively surrounding the bolts and piled up along the same bolts; a suspension member having a peripheral wall defining an upper opening and a lower opening and a bottom plate protruding inwardly therefrom and being supported by the supporting members. The supporting members are being detachable and replaceable so that the wall of suspension member can be raised or lowered thus enabling the cover of conduit hole to be adjusted to a level with a changing road surface.
Abstract:
Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated the substrate by a collar dielectric layer. A trench top oxide (TTO) layer is disposed on the first conductive layer. A vertical transistor is disposed over the TTO layer. The vertical transistor comprises a gate dielectric layer disposed on the sidewalls of the upper portion of the trench, and a metal gate disposed in the upper portion of the trench.