发明授权
US07869239B2 Layout structure of bit line sense amplifiers for a semiconductor memory device
有权
用于半导体存储器件的位线读出放大器的布局结构
- 专利标题: Layout structure of bit line sense amplifiers for a semiconductor memory device
- 专利标题(中): 用于半导体存储器件的位线读出放大器的布局结构
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申请号: US12078724申请日: 2008-04-03
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公开(公告)号: US07869239B2公开(公告)日: 2011-01-11
- 发明人: Young-Sun Min , Kyu-Chan Lee , Chul-Woo Yi , Jong-Hyun Choi
- 申请人: Young-Sun Min , Kyu-Chan Lee , Chul-Woo Yi , Jong-Hyun Choi
- 申请人地址: KR Suwon-si, Gyeonggi-do
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Suwon-si, Gyeonggi-do
- 代理机构: Lee & Morse, P.C.
- 优先权: KR10-2007-0033135 20070404
- 主分类号: G11C5/02
- IPC分类号: G11C5/02
摘要:
A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.
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