发明授权
US07869239B2 Layout structure of bit line sense amplifiers for a semiconductor memory device 有权
用于半导体存储器件的位线读出放大器的布局结构

Layout structure of bit line sense amplifiers for a semiconductor memory device
摘要:
A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.
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