Invention Grant
- Patent Title: Semiconductor device having laminated structure
- Patent Title (中): 具有层叠结构的半导体装置
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Application No.: US11215121Application Date: 2005-08-31
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Publication No.: US07875980B2Publication Date: 2011-01-25
- Inventor: Toshikazu Imaoka , Ryosuke Usui
- Applicant: Toshikazu Imaoka , Ryosuke Usui
- Applicant Address: JP Osaka
- Assignee: Sanyo Electric Co., Ltd.
- Current Assignee: Sanyo Electric Co., Ltd.
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2004-253998 20040901
- Main IPC: H01L23/12
- IPC: H01L23/12

Abstract:
A technique for reducing the size of a semiconductor device is provided. A semiconductor device comprises a base, a semiconductor chip, a chip component, an insulating base, a wiring pattern, a via plug, an external lead-out electrode, a recess, and a resin. The insulating base has a multi-layer structure formed by laminating a plurality of insulator films. The semiconductor chip and the chip component are mounted on the base and embedded in the insulating base. A recess is formed on the surface of the semiconductor device and reaches down to any of wiring conductor layers. The semiconductor chip and the chip component are mounted on the recess.
Public/Granted literature
- US20060043606A1 Semiconductor device having laminated structure Public/Granted day:2006-03-02
Information query
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