Invention Grant
US07881125B2 Power reduction in a content addressable memory having programmable interconnect structure
有权
具有可编程互连结构的内容可寻址存储器中的功率降低
- Patent Title: Power reduction in a content addressable memory having programmable interconnect structure
- Patent Title (中): 具有可编程互连结构的内容可寻址存储器中的功率降低
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Application No.: US12873122Application Date: 2010-08-31
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Publication No.: US07881125B2Publication Date: 2011-02-01
- Inventor: Maheshwaran Srinivasan , Varadarajan Srinivasan , Sandeep Khanna , Sachin Joshi , Mark Birman
- Applicant: Maheshwaran Srinivasan , Varadarajan Srinivasan , Sandeep Khanna , Sachin Joshi , Mark Birman
- Applicant Address: US CA Santa Clara
- Assignee: NetLogic Microsystems, Inc.
- Current Assignee: NetLogic Microsystems, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Mahamedi Paradice Kreisman LLP
- Agent William L. Paradice, III
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous.
Public/Granted literature
- US20100321970A1 CONTENT ADDRESSABLE MEMORY HAVING PROGRAMMABLE INTERCONNECT STRUCTURE Public/Granted day:2010-12-23
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