Invention Grant
- Patent Title: Chip-stacked package structure and method for manufacturing the same
- Patent Title (中): 芯片堆叠封装结构及其制造方法
-
Application No.: US12648655Application Date: 2009-12-29
-
Publication No.: US07884486B2Publication Date: 2011-02-08
- Inventor: Yu-Tang Pan , Shih-Wen Chou
- Applicant: Yu-Tang Pan , Shih-Wen Chou
- Applicant Address: TW Hsinchu
- Assignee: Chipmos Technology Inc.
- Current Assignee: Chipmos Technology Inc.
- Current Assignee Address: TW Hsinchu
- Agency: Thomas, Kayden, Horstemeyer & Risley, LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40

Abstract:
A chip stacked package structure and applications are provided. The chip-stacked package structure includes a main substrate, a baseboard substrate, and a molding compound. The main substrate has a substrate and a first chip. The substrate has a first surface and a second surface opposite to the first surface. The first chip is disposed on the first surface and electrically connected to the substrate via first bumps. The baseboard substrate has a third surface and a fourth surface faced towards the substrate. The baseboard substrate includes a core layer having a plurality of first through holes and a first accommodation space in which the first chip is received. The second chip is disposed on the third surface of the baseboard substrate. The molding compound is used to encapsulate the main substrate, and the baseboard substrate.
Public/Granted literature
- US20100096741A1 Chip-Stacked Package Structure and Method for Manufacturing the Same Public/Granted day:2010-04-22
Information query
IPC分类: