-
公开(公告)号：US07884486B2
公开(公告)日：2011-02-08
申请号：US12648655
申请日：2009-12-29
Applicant: Yu-Tang Pan , Shih-Wen Chou
Inventor： Yu-Tang Pan , Shih-Wen Chou
CPC classification number: H01L25/0657 , H01L23/3128 , H01L24/73 , H01L2224/0401 , H01L2224/06135 , H01L2224/06136 , H01L2224/16 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2924/15311 , H01L2924/19107 , H01L2924/00014 , H01L2924/00012 , H01L2224/48227 , H01L2924/00
Abstract: A chip stacked package structure and applications are provided. The chip-stacked package structure includes a main substrate, a baseboard substrate, and a molding compound. The main substrate has a substrate and a first chip. The substrate has a first surface and a second surface opposite to the first surface. The first chip is disposed on the first surface and electrically connected to the substrate via first bumps. The baseboard substrate has a third surface and a fourth surface faced towards the substrate. The baseboard substrate includes a core layer having a plurality of first through holes and a first accommodation space in which the first chip is received. The second chip is disposed on the third surface of the baseboard substrate. The molding compound is used to encapsulate the main substrate, and the baseboard substrate.
Abstract translation: 提供了芯片堆叠的封装结构和应用。 芯片堆叠的封装结构包括主基板，基板基板和模塑料。 主基板具有基板和第一芯片。 基板具有与第一表面相对的第一表面和第二表面。 第一芯片设置在第一表面上并且经由第一凸块与基板电连接。 基板基板具有面向基板的第三表面和第四表面。 基板基板包括具有多个第一通孔的芯层和接收第一芯片的第一容纳空间。 第二芯片设置在基板的第三表面上。 模塑料用于封装主基板和基板基板。
-
Patent Agency Ranking
公开(公告)号：US20100155929A1
公开(公告)日：2010-06-24
申请号：US12713333
申请日：2010-02-26
Applicant: Chun-Ying Lin , Yu-Tang Pan , Shih-Wen Chou , Geng-Shin Shen
Inventor： Chun-Ying Lin , Yu-Tang Pan , Shih-Wen Chou , Geng-Shin Shen
IPC: H01L25/065 , H01L23/52
CPC classification number: H01L25/0657 , H01L23/3121 , H01L24/73 , H01L2224/0401 , H01L2224/04073 , H01L2224/06135 , H01L2224/06136 , H01L2224/16145 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/4824 , H01L2224/4918 , H01L2224/731 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2224/83102 , H01L2224/92125 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06582 , H01L2225/06589 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer.
Abstract translation: 提供了芯片堆叠封装结构和应用，其中芯片堆叠封装结构包括衬底，第一芯片，图案化电路层和第二芯片。 衬底具有第一表面和相对的第二表面。 具有第一有源区和相对的第一后表面的第一芯片通过倒装芯片接合工艺电连接到衬底的第一表面。 设置在电介质层上的图案化电路层通过接合线电连接到基板。 设置在图案化电路层上的第二芯片具有形成在第二有源区上的第二有源区和多个第二焊盘，其中第二焊盘与图案化电路层电连接。
-
公开(公告)号：US20100096741A1
公开(公告)日：2010-04-22
申请号：US12648655
申请日：2009-12-29
Applicant: Yu-Tang Pan , Shih-Wen Chou
Inventor： Yu-Tang Pan , Shih-Wen Chou
IPC: H01L25/065 , H01L21/50 , H01L23/52
CPC classification number: H01L25/0657 , H01L23/3128 , H01L24/73 , H01L2224/0401 , H01L2224/06135 , H01L2224/06136 , H01L2224/16 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2924/15311 , H01L2924/19107 , H01L2924/00014 , H01L2924/00012 , H01L2224/48227 , H01L2924/00
Abstract: A chip stacked package structure and applications are provided. The chip-stacked package structure includes a main substrate, a baseboard substrate, and a molding compound. The main substrate has a substrate and a first chip. The substrate has a first surface and a second surface opposite to the first surface. The first chip is disposed on the first surface and electrically connected to the substrate via first bumps. The baseboard substrate has a third surface and a fourth surface faced towards the substrate. The baseboard substrate includes a core layer having a plurality of first through holes and a first accommodation space in which the first chip is received. The second chip is disposed on the third surface of the baseboard substrate. The molding compound is used to encapsulate the main substrate, and the baseboard substrate.
Abstract translation: 提供了芯片堆叠的封装结构和应用。 芯片堆叠的封装结构包括主基板，基板基板和模塑料。 主基板具有基板和第一芯片。 基板具有与第一表面相对的第一表面和第二表面。 第一芯片设置在第一表面上并且经由第一凸块与基板电连接。 基板基板具有面向基板的第三表面和第四表面。 基板基板包括具有多个第一通孔的芯层和接收第一芯片的第一容纳空间。 第二芯片设置在基板的第三表面上。 模塑料用于封装主基板和基板基板。
-
公开(公告)号：US07696629B2
公开(公告)日：2010-04-13
申请号：US11872205
申请日：2007-10-15
Applicant: Chun-Ying Lin , Yu-Tang Pan , Shih-Wen Chou , Geng-Shin Shen
Inventor： Chun-Ying Lin , Yu-Tang Pan , Shih-Wen Chou , Geng-Shin Shen
CPC classification number: H01L25/0657 , H01L23/3121 , H01L24/73 , H01L2224/0401 , H01L2224/04073 , H01L2224/06135 , H01L2224/06136 , H01L2224/16145 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/4824 , H01L2224/4918 , H01L2224/731 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2224/83102 , H01L2224/92125 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06582 , H01L2225/06589 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer.
Abstract translation: 提供了芯片堆叠封装结构和应用，其中芯片堆叠封装结构包括衬底，第一芯片，图案化电路层和第二芯片。 衬底具有第一表面和相对的第二表面。 具有第一有源区和相对的第一后表面的第一芯片通过倒装芯片接合工艺电连接到衬底的第一表面。 设置在电介质层上的图案化电路层通过接合线电连接到基板。 设置在图案化电路层上的第二芯片具有形成在第二有源区上的第二有源区和多个第二焊盘，其中第二焊盘与图案化电路层电连接。
-
公开(公告)号：US20080265400A1
公开(公告)日：2008-10-30
申请号：US11872169
申请日：2007-10-15
Applicant: Yu-Tang Pan , Shih-Wen Chou , Chun-Ying Lin
Inventor： Yu-Tang Pan , Shih-Wen Chou , Chun-Ying Lin
CPC classification number: H01L25/0657 , H01L23/3128 , H01L24/73 , H01L2224/0401 , H01L2224/06135 , H01L2224/06136 , H01L2224/16 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2924/15311 , H01L2924/19107 , H01L2924/00014 , H01L2924/00012 , H01L2224/48227 , H01L2924/00
Abstract: A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, circuit board and a second chip. The substrate has a first surface and an opposite second surface. The first chip having a first active surface and an opposite first rear surface is electrically connected to first surface of substrate serving by a flip chip bonding process. The circuit board has a dielectric layer set on the first rear surface and a patterned conductive layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned conductive layer has a plurality of second pads formed on a second active surface thereof and eclectically connected to the patterned conductive layer.
Abstract translation: 提供了一种芯片堆叠封装结构和应用，其中芯片堆叠封装结构包括衬底，第一芯片，电路板和第二芯片。 衬底具有第一表面和相对的第二表面。 具有第一有源表面和相对的第一后表面的第一芯片通过倒装芯片接合工艺电连接到基板的第一表面。 电路板具有设置在第一后表面上的电介质层，并且设置在电介质层上的图案化导电层经由接合线电连接至基板。 设置在图案化导电层上的第二芯片具有形成在其第二有源表面上的多个第二焊盘，并且折叠地连接到图案化的导电层。
-
公开(公告)号：US20080265397A1
公开(公告)日：2008-10-30
申请号：US11872205
申请日：2007-10-15
Applicant: Chun-Ying Lin , Yu-Tang Pan , Shih-Wen Chou , Geng-Shin Shen
Inventor： Chun-Ying Lin , Yu-Tang Pan , Shih-Wen Chou , Geng-Shin Shen
IPC: H01L23/49
CPC classification number: H01L25/0657 , H01L23/3121 , H01L24/73 , H01L2224/0401 , H01L2224/04073 , H01L2224/06135 , H01L2224/06136 , H01L2224/16145 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/4824 , H01L2224/4918 , H01L2224/731 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2224/83102 , H01L2224/92125 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06582 , H01L2225/06589 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer.
Abstract translation: 提供了芯片堆叠封装结构和应用，其中芯片堆叠封装结构包括衬底，第一芯片，图案化电路层和第二芯片。 衬底具有第一表面和相对的第二表面。 具有第一有源区和相对的第一后表面的第一芯片通过倒装芯片接合工艺电连接到衬底的第一表面。 设置在电介质层上的图案化电路层通过接合线电连接到基板。 设置在图案化电路层上的第二芯片具有形成在第二有源区上的第二有源区和多个第二焊盘，其中第二焊盘与图案化电路层电连接。
-
-
-
-
-
Search Results
6
records
(took 0.012 seconds)
