公开(公告)号：US20120241935A1

公开(公告)日：2012-09-27

申请号：US13205649

申请日：2011-08-09

申请人： Shih-Wen Chou ,  Yu-Tang Pan

发明人： Shih-Wen Chou ,  Yu-Tang Pan

IPC分类号： H01L23/34

CPC分类号： H01L23/49816 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49833 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package-on-package structure includes first and second package structures and bumps. The first package structure includes a carrier, a chip configured on the carrier, a heat spreader, and an encapsulant. The chip is electrically connected to the carrier through conductive wires. The heat spreader includes a support portion located on the chip and connection portions located respectively at two opposite sides of the support portion. The heat spreader has a circuit layer thereon, covers the chip and the conductive wires, and electrically connects the carrier through the circuit layer on the connecting portions. The encapsulant encapsulates the chip, the conductive wires, a portion of the heat spreader, and a portion of the carrier. The bumps are configured on the support portion. The second package structure is configured on the first package structure and is electrically connected to the first package structure through the bumps.

摘要翻译： 包装封装结构包括第一和第二封装结构和凸块。 第一封装结构包括载体，配置在载体上的芯片，散热器和密封剂。 芯片通过导线与载体电连接。 散热器包括位于芯片上的支撑部分和分别位于支撑部分的相对两侧的连接部分。 散热器在其上具有电路层，覆盖芯片和导线，并且通过连接部分上的电路层将载体电连接。 密封剂封装芯片，导线，散热器的一部分和载体的一部分。 凸起构造在支撑部分上。 第二封装结构被配置在第一封装结构上，并且通过凸块与第一封装结构电连接。

公开(公告)号：US07884486B2

公开(公告)日：2011-02-08

申请号：US12648655

申请日：2009-12-29

申请人： Yu-Tang Pan ,  Shih-Wen Chou

发明人： Yu-Tang Pan ,  Shih-Wen Chou

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/48227 ,  H01L2924/00

摘要： A chip stacked package structure and applications are provided. The chip-stacked package structure includes a main substrate, a baseboard substrate, and a molding compound. The main substrate has a substrate and a first chip. The substrate has a first surface and a second surface opposite to the first surface. The first chip is disposed on the first surface and electrically connected to the substrate via first bumps. The baseboard substrate has a third surface and a fourth surface faced towards the substrate. The baseboard substrate includes a core layer having a plurality of first through holes and a first accommodation space in which the first chip is received. The second chip is disposed on the third surface of the baseboard substrate. The molding compound is used to encapsulate the main substrate, and the baseboard substrate.

摘要翻译： 提供了芯片堆叠的封装结构和应用。 芯片堆叠的封装结构包括主基板，基板基板和模塑料。 主基板具有基板和第一芯片。 基板具有与第一表面相对的第一表面和第二表面。 第一芯片设置在第一表面上并且经由第一凸块与基板电连接。 基板基板具有面向基板的第三表面和第四表面。 基板基板包括具有多个第一通孔的芯层和接收第一芯片的第一容纳空间。 第二芯片设置在基板的第三表面上。 模塑料用于封装主基板和基板基板。

公开(公告)号：US07514299B2

公开(公告)日：2009-04-07

申请号：US11530165

申请日：2006-09-08

申请人： Chun-Hung Lin ,  Shih-Wen Chou ,  Yu-Tang Pan

发明人： Chun-Hung Lin ,  Shih-Wen Chou ,  Yu-Tang Pan

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L23/49816 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A manufacturing method of a chip package structure is provided. A circuit substrate having a first surface, a second surface, and a through hole connecting the first surface and the second surface is provided. A chip having an active surface and bonding pads disposed on the active surface is provided. The chip is fixed on the circuit substrate, wherein the second surface is opposite to the active surface and the bonding pads are exposed to the through hole. Bonding wires connecting the bonding pads and the first surface are formed through the through hole. A film having an opening is formed on the first surface. The bonding wires, the bonding pads, the through hole, and part of the first surface are exposed by the opening. An encapsulant is formed to encapsulate part of the active surface, the bonding wires, and part of the first surface. The film is removed.

摘要翻译： 提供了一种芯片封装结构的制造方法。 提供具有第一表面，第二表面和连接第一表面和第二表面的通孔的电路基板。 提供具有有源表面的芯片和设置在有源表面上的接合焊盘。 芯片固定在电路基板上，其中第二表面与有源表面相对，并且焊盘暴露于通孔。 通过通孔形成连接接合焊盘和第一表面的接合线。 具有开口的膜形成在第一表面上。 接合线，接合焊盘，通孔和第一表面的一部分由开口露出。 形成密封剂以封装部分活性表面，接合线和第一表面的一部分。 电影被删除。

公开(公告)号：US20080142947A1

公开(公告)日：2008-06-19

申请号：US11746064

申请日：2007-05-09

申请人： Yu-Tang Pan ,  Men-Shew Liu ,  Shih-Wen Chou

发明人： Yu-Tang Pan ,  Men-Shew Liu ,  Shih-Wen Chou

IPC分类号： H01L23/48 ,  H01L21/00

CPC分类号： H01L23/49531 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0554 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A chip package including a metal layer, a film-like circuit layer, a chip, a lead matrix and an encapsulant is provided. The film-like circuit layer disposed on the metal layer includes an insulating film disposed on the metal layer and a circuit layer disposed on the insulating film. The circuit layer has a plurality of conductive traces. The chip disposed above the metal layer is electrically connected to the conductive traces. The lead matrix having a plurality of leads is disposed outside the chip. At least part of the leads are electrically connected to the conductive traces. The encapsulant at least encapsulates the chip, the film-like circuit layer, at least part of the leads, and at least part of the metal layer.

摘要翻译： 提供了包括金属层，膜状电路层，芯片，引线基体和密封剂的芯片封装。 设置在金属层上的膜状电路层包括设置在金属层上的绝缘膜和设置在绝缘膜上的电路层。 电路层具有多个导电迹线。 设置在金属层上方的芯片电连接到导电迹线。 具有多个引线的引线矩阵设置在芯片外部。 引线的至少一部分电连接到导电迹线。 密封剂至少封装芯片，膜状电路层，引线的至少一部分以及金属层的至少一部分。

公开(公告)号：US08148827B2

公开(公告)日：2012-04-03

申请号：US12832223

申请日：2010-07-08

申请人： Yu-Tang Pan ,  Shih-Wen Chou

发明人： Yu-Tang Pan ,  Shih-Wen Chou

IPC分类号： H01L23/49

CPC分类号： H01L24/49 ,  H01L23/3121 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： The present invention relates to a quad flat no lead (QFN) package is provided. In the invention, a plurality of first pads are disposed outside an extension area of a conductive circuit layer, and a plurality of second pads are disposed inside a die bonding area of the conductive circuit layer, wherein the extension area surrounds the die bonding area. First ends of a plurality of traces are connected to the second pads, and second ends of the traces are located in the extension area. An insulating layer fills at least the die bonding area and the extension area, and exposes top surfaces and bottom surfaces of the second pads. A chip is mounted at the die bonding area and a plurality of wires electrically connect the chip to the first pads and the second ends of the traces respectively. An encapsulation material is used to cover the conductive circuit layer, the chip and the wires. Whereby, the package of the invention can have more inputs/outputs terminals, and the insulating layer can prevent moisture permeation from corroding the joints between the wires and the first pads and the second ends of the traces, thus increasing the reliability of the package of the invention.

摘要翻译： 本发明涉及一种四边形无铅（QFN）封装。 在本发明中，多个第一焊盘设置在导电电路层的延伸区域的外侧，并且多个第二焊盘设置在导电电路层的管芯接合区域的内部，其中延伸区域围绕管芯接合区域。 多个迹线的第一端连接到第二焊盘，并且迹线的第二端位于扩展区域中。 绝缘层至少填充芯片接合区域和延伸区域，并且暴露第二焊盘的顶表面和底表面。 芯片安装在管芯接合区域，并且多条电线分别将芯片电连接到第一焊盘和迹线的第二端。 封装材料用于覆盖导电电路层，芯片和电线。 由此，本发明的封装可以具有更多的输入/输出端子，并且绝缘层可以防止水分渗透腐蚀电线与第一焊盘和迹线的第二端之间的接合，从而增加封装的可靠性 本发明。

公开(公告)号：US20080265397A1

公开(公告)日：2008-10-30

申请号：US11872205

申请日：2007-10-15

申请人： Chun-Ying Lin ,  Yu-Tang Pan ,  Shih-Wen Chou ,  Geng-Shin Shen

发明人： Chun-Ying Lin ,  Yu-Tang Pan ,  Shih-Wen Chou ,  Geng-Shin Shen

IPC分类号： H01L23/49

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04073 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/4918 ,  H01L2224/731 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer.

摘要翻译： 提供了芯片堆叠封装结构和应用，其中芯片堆叠封装结构包括衬底，第一芯片，图案化电路层和第二芯片。 衬底具有第一表面和相对的第二表面。 具有第一有源区和相对的第一后表面的第一芯片通过倒装芯片接合工艺电连接到衬底的第一表面。 设置在电介质层上的图案化电路层通过接合线电连接到基板。 设置在图案化电路层上的第二芯片具有形成在第二有源区上的第二有源区和多个第二焊盘，其中第二焊盘与图案化电路层电连接。

公开(公告)号：US07696629B2

公开(公告)日：2010-04-13

申请号：US11872205

申请日：2007-10-15

申请人： Chun-Ying Lin ,  Yu-Tang Pan ,  Shih-Wen Chou ,  Geng-Shin Shen

发明人： Chun-Ying Lin ,  Yu-Tang Pan ,  Shih-Wen Chou ,  Geng-Shin Shen

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04073 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/4918 ,  H01L2224/731 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer.

摘要翻译： 提供了芯片堆叠封装结构和应用，其中芯片堆叠封装结构包括衬底，第一芯片，图案化电路层和第二芯片。 衬底具有第一表面和相对的第二表面。 具有第一有源区和相对的第一后表面的第一芯片通过倒装芯片接合工艺电连接到衬底的第一表面。 设置在电介质层上的图案化电路层通过接合线电连接到基板。 设置在图案化电路层上的第二芯片具有形成在第二有源区上的第二有源区和多个第二焊盘，其中第二焊盘与图案化电路层电连接。

公开(公告)号：US20080265400A1

公开(公告)日：2008-10-30

申请号：US11872169

申请日：2007-10-15

申请人： Yu-Tang Pan ,  Shih-Wen Chou ,  Chun-Ying Lin

发明人： Yu-Tang Pan ,  Shih-Wen Chou ,  Chun-Ying Lin

IPC分类号： H01L23/04 ,  H01L21/00

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/48227 ,  H01L2924/00

摘要： A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, circuit board and a second chip. The substrate has a first surface and an opposite second surface. The first chip having a first active surface and an opposite first rear surface is electrically connected to first surface of substrate serving by a flip chip bonding process. The circuit board has a dielectric layer set on the first rear surface and a patterned conductive layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned conductive layer has a plurality of second pads formed on a second active surface thereof and eclectically connected to the patterned conductive layer.

摘要翻译： 提供了一种芯片堆叠封装结构和应用，其中芯片堆叠封装结构包括衬底，第一芯片，电路板和第二芯片。 衬底具有第一表面和相对的第二表面。 具有第一有源表面和相对的第一后表面的第一芯片通过倒装芯片接合工艺电连接到基板的第一表面。 电路板具有设置在第一后表面上的电介质层，并且设置在电介质层上的图案化导电层经由接合线电连接至基板。 设置在图案化导电层上的第二芯片具有形成在其第二有源表面上的多个第二焊盘，并且折叠地连接到图案化的导电层。

公开(公告)号：US20080093606A1

公开(公告)日：2008-04-24

申请号：US11762067

申请日：2007-06-13

申请人： Yu-Tang Pan ,  Shih-Wen Chou ,  Men-Shew Liu

发明人： Yu-Tang Pan ,  Shih-Wen Chou ,  Men-Shew Liu

IPC分类号： H01L33/00 ,  H01L21/00

CPC分类号： H01L33/486 ,  H01L24/97 ,  H01L33/62 ,  H01L33/64 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method for manufacturing a light emitting chip package includes bonding a patterned metal plate having at least a thermal enhanced plate and many contacts around the same to a substrate and bonding a film-like circuit layer to the patterned metal plate. Many conductive wires are formed to connect the film-like circuit layer and the contacts. Thereafter, at least a first molding is formed on the substrate to encapsulate the patterned metal plate, the conductive wires and a portion of the film-like circuit layer. At least one light emitting chip disposed on the film-like circuit layer exposed by the first molding has many bumps to which the light emitting chip and the film-like circuit layer are electrically connected. A cutting process is performed to form at least one light emitting chip package, and the substrate is removed. Therefore, heat dissipation efficiency of the light emitting chip package can be improved.

摘要翻译： 一种发光芯片封装的制造方法，其特征在于，将具有至少具有热增强板的图案化金属板和与其接触的多个触点结合，并将膜状电路层与图案化的金属板接合。 形成许多导线以连接膜状电路层和触点。 此后，在基板上形成至少第一模制件，以封装图案化的金属板，导电线和薄膜状电路层的一部分。 设置在通过第一模制件露出的膜状电路层上的至少一个发光芯片具有多个凸起，发光芯片和膜状电路层电连接到该凸起。 执行切割处理以形成至少一个发光芯片封装，并且去除衬底。 因此，可以提高发光芯片封装的散热效率。

公开(公告)号：US20070080466A1

公开(公告)日：2007-04-12

申请号：US11326789

申请日：2006-01-05

申请人： Shih-Wen Chou ,  Chun-Hung Lin ,  Wu-Chang Tu ,  Yu-Tang Pan

发明人： Shih-Wen Chou ,  Chun-Hung Lin ,  Wu-Chang Tu ,  Yu-Tang Pan

IPC分类号： H01L23/52

CPC分类号： H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/10 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85186 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A universal chip package structure including a carrier, a chip, a plurality of bonding wires, and a molding compound is provided. The carrier has a plurality of through holes, a carrying surface, and a back surface corresponding to the carrying surface. The back surface has a plurality of contacts around the through holes. The chip with an active surface and a plurality of bonding pads on the active surface is disposed on the carrying surface. The active surface is attached to the carrying surface and the through holes expose the bonding pads. The bonding wires go through the through holes to electrically connect with the bonding pads and the contacts. In addition, the shape and size of the molding compound can be adjusted for covering the chip, the contacts, and the bonding wires.

摘要翻译： 提供了包括载体，芯片，多个接合线和模塑料的通用芯片封装结构。 载体具有多个通孔，承载表面和对应于承载表面的后表面。 后表面具有围绕通孔的多个触点。 具有活性表面的芯片和有源表面上的多个接合焊盘设置在承载表面上。 活性表面附着在承载表面上，通孔露出接合垫。 接合线穿过通孔，以与接合焊盘和触点电连接。 此外，可以调整模塑料的形状和尺寸以覆盖芯片，触点和接合线。