发明授权
US07885046B1 Low capacitance ESD protection structure for high speed input pins
有权
用于高速输入引脚的低电容ESD保护结构
- 专利标题: Low capacitance ESD protection structure for high speed input pins
- 专利标题(中): 用于高速输入引脚的低电容ESD保护结构
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申请号: US11869805申请日: 2007-10-10
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公开(公告)号: US07885046B1公开(公告)日: 2011-02-08
- 发明人: Antonio Gallerano , Cheng-Hsiung Huang , Jeffrey T. Watt
- 申请人: Antonio Gallerano , Cheng-Hsiung Huang , Jeffrey T. Watt
- 申请人地址: US CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Ward & Olivo
- 主分类号: H02H9/00
- IPC分类号: H02H9/00 ; H02H1/00
摘要:
A conventional ESD protection circuit comprises an SCR and a first diode connected in series between ground and a node or pad to be protected and a second diode connected between ground and the node to be protected. An anode of the first diode and a cathode of the second diode are connected to the node to be protected. In one embodiment of the invention, the capacitance of the second diode is reduced by forming the second diode from a PN junction between a heavily doped region of one conductivity type and a substrate region instead of a well region of the opposite conductivity type. The reduction in the capacitance of the second diode makes it possible to increase the size of the first diode and SCR, thereby decreasing their resistance, while keeping the total capacitance of the ESD circuit at or below the capacitance of the prior art ESD circuit. A second embodiment of an ESD protection comprises an SCR and a first diode connected in series between ground and node to be protected and second and third diodes connected in series between ground and the node to be protected with the anode of the second diode connected to ground. Again, the capacitance of the second diode is reduced by forming the diode from a PN junction between a heavily doped region of one conductivity type and a substrate region of the other conductivity type.
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