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1.发明授权Method and apparatus for improving triggering uniformity of snapback electrostatic discharge protection devices 有权用于提高闪回静电放电保护装置的触发均匀性的方法和装置公开(公告)号：US08946001B1
公开(公告)日：2015-02-03
申请号：US13349531
申请日：2012-01-12
申请人： Jeffrey T. Watt , Antonio Gallerano
发明人： Jeffrey T. Watt , Antonio Gallerano
IPC分类号： H01L21/332
CPC分类号： H01L27/0277
摘要： An electrostatic discharge (ESD) protection circuit includes a first array of transistors, having source and drain doped with a first type of material, arranged in parallel in a first block, and a second array of transistors, having source and drain doped with the first type of material, arranged in parallel in a second block. The ESD protection circuit also includes an active region between the first and second array of transistors doped with a second type of material that is complementary to the first type of material.
摘要翻译： 静电放电（ESD）保护电路包括：第一晶体管阵列，其具有掺杂有第一类型材料的源极和漏极，并排布置在第一块中;以及第二晶体管阵列，其具有源极和漏极掺杂有第一 材料类型，平行布置在第二块中。 ESD保护电路还包括掺杂有与第一类型材料互补的第二类型材料的第一和第二晶体阵列之间的有源区。
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公开(公告)号：US07990664B1
公开(公告)日：2011-08-02
申请号：US11639792
申请日：2006-12-14
CPC分类号： H01L27/0277
摘要： An ESD protection circuit is integrated into the core of an FPGA in a distributed fashion coupling the bodies of one or more transistors to the power supply pin and/or the ground pin of the FPGA. The ESD protection circuit includes one or more positive discharge paths and one or more negative discharge paths. In the case of a positive ESD event, the positive discharge paths are on and the negative discharge paths are off. In the case of a negative ESD event, the positive discharge paths are off and the negative discharge paths are on. In either event, the bodies of the transistors track the voltages at the power supply pin and/or the ground pin to protect the core from being by damaged by electrostatic discharge.
摘要翻译： ESD保护电路以分布式的方式集成到FPGA的核心中，将一个或多个晶体管的主体耦合到FPGA的电源引脚和/或接地引脚。 ESD保护电路包括一个或多个正放电路径和一个或多个负排出路径。 在正的ESD事件的情况下，正的放电路径导通，负的放电路径关闭。 在负ESD事件的情况下，正的放电路径关闭，负的放电路径导通。 在任一情况下，晶体管的主体跟踪电源引脚和/或接地引脚上的电压，以保护芯不被静电放电损坏。
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公开(公告)号：US08116048B1
公开(公告)日：2012-02-14
申请号：US12577547
申请日：2009-10-12
IPC分类号： H02H3/22
CPC分类号： H02H3/22
摘要： In a conventional differential output circuit, the output terminals are connected to the drains of a differential pair of transistors and the sources of the transistors are connected together at a first node. The bodies of the transistors are connected to a second node having a potential different from that of the first node. In the event of a HBM ESD event, discharge may take place through the differential transistors, leading to destruction of one of them. To reduce the likelihood of such discharge, in a preferred embodiment, switches are provided to connect the body of each of the differential transistors to the first node when an ESD event is sensed. In an alternative embodiment, a switch is provided to connect the first node to the second node when an ESD event is sensed.
摘要翻译： 在传统的差分输出电路中，输出端连接到差分对晶体管的漏极，晶体管的源极在第一个节点连接在一起。 晶体管的主体连接到具有不同于第一节点的电位的第二节点。 在HBM ESD事件发生的情况下，放电可能通过差分晶体管发生，从而导致其中的一个被破坏。 为了降低这种放电的可能性，在优选实施例中，提供开关以在感测到ESD事件时将每个差分晶体管的主体连接到第一节点。 在替代实施例中，当感测到ESD事件时，提供开关来将第一节点连接到第二节点。
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公开(公告)号：US07955923B1
公开(公告)日：2011-06-07
申请号：US12845337
申请日：2010-07-28
IPC分类号： H01L21/8238
CPC分类号： H01L29/6659 , H01L27/0277 , H01L29/1083 , H01L29/1087 , H01L2924/14
摘要： A trigger circuit is provided for a pull-down device by connecting a diode between the I/O pad and the body of the pull-down device. In one embodiment, the pull-down device is formed as a plurality of discrete transistors in a single well. The drain of each transistor is connected through a ballast resistor to the I/O pad; and the source of each transistor is connected through a ballast resistor to ground. The trigger circuit is a diode formed in a different well from that of the transistors. The cathode of the diode is connected to the I/O pad and the anode is connected to the transistor well through a center tap located between the transistors. Preferably, the transistors are NMOS transistors formed in a P-well. Advantageously, the diode is an N+/PLDD diode. Alternatively, the diode is an N+/P diode where the P region is formed by an ESD implant. In other embodiments the diode is formed in the same well as the transistors. In these embodiments, either an N+/PLDD diode or an implanted diode is formed in place of one of the transistors.
摘要翻译： 通过在I / O焊盘和下拉装置的主体之间连接二极管，为下拉装置提供触发电路。 在一个实施例中，下拉装置形成为单个阱中的多个分立晶体管。 每个晶体管的漏极通过镇流电阻连接到I / O焊盘; 并且每个晶体管的源极通过镇流电阻器连接到地。 触发电路是形成在与晶体管不同的阱中的二极管。 二极管的阴极连接到I / O焊盘，阳极通过位于晶体管之间的中心抽头连接到晶体管。 优选地，晶体管是形成在P阱中的NMOS晶体管。 有利地，二极管是N + / PLDD二极管。 或者，二极管是N + / P二极管，其中P区由ESD注入形成。 在其他实施例中，二极管形成在与晶体管相同的阱中。 在这些实施例中，形成N + / PLDD二极管或注入二极管代替晶体管之一。
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公开(公告)号：US07885046B1
公开(公告)日：2011-02-08
申请号：US11869805
申请日：2007-10-10
CPC分类号： H01L27/0262
摘要： A conventional ESD protection circuit comprises an SCR and a first diode connected in series between ground and a node or pad to be protected and a second diode connected between ground and the node to be protected. An anode of the first diode and a cathode of the second diode are connected to the node to be protected. In one embodiment of the invention, the capacitance of the second diode is reduced by forming the second diode from a PN junction between a heavily doped region of one conductivity type and a substrate region instead of a well region of the opposite conductivity type. The reduction in the capacitance of the second diode makes it possible to increase the size of the first diode and SCR, thereby decreasing their resistance, while keeping the total capacitance of the ESD circuit at or below the capacitance of the prior art ESD circuit. A second embodiment of an ESD protection comprises an SCR and a first diode connected in series between ground and node to be protected and second and third diodes connected in series between ground and the node to be protected with the anode of the second diode connected to ground. Again, the capacitance of the second diode is reduced by forming the diode from a PN junction between a heavily doped region of one conductivity type and a substrate region of the other conductivity type.
摘要翻译： 传统的ESD保护电路包括一个SCR和一个第一二极管，串联连接在接地和待保护的节点或焊盘之间，第二个二极管连接在地和待保护的节点之间。 第一二极管的阳极和第二二极管的阴极连接到要保护的节点。 在本发明的一个实施例中，通过从一个导电类型的重掺杂区域和衬底区域之间的PN结形成第二二极管而不是相反导电类型的阱区域来减小第二二极管的电容。 第二二极管的电容的减小使得可以增加第一二极管和SCR的尺寸，从而降低它们的电阻，同时将ESD电路的总电容保持在现有技术ESD电路的电容或低于现有技术ESD电路的电容。 ESD保护的第二实施例包括SCR和第一二极管，其串联连接在待保护的接地端和节点之间，并且第二和第三二极管串联连接在接地和节点之间，第二二极管的阳极连接到地 。 再次，通过从一个导电类型的重掺杂区域和另一个导电类型的衬底区域之间的PN结形成二极管来减小第二二极管的电容。
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公开(公告)号：US08619398B1
公开(公告)日：2013-12-31
申请号：US13365579
申请日：2012-02-03
IPC分类号： H02H3/22
CPC分类号： H02H3/22
摘要： In a conventional differential output circuit, the output terminals are connected to the drains of a differential pair of transistors and the sources of the transistors are connected together at a first node. The bodies of the transistors are connected to a second node having a potential different from that of the first node. In the event of a HBM ESD event, discharge may take place through the differential transistors, leading to destruction of one of them. To reduce the likelihood of such discharge, in a preferred embodiment, switches are provided to connect the body of each of the differential transistors to the first node when an ESD event is sensed. In an alternative embodiment, a switch is provided to connect the first node to the second node when an ESD event is sensed.
摘要翻译： 在传统的差分输出电路中，输出端连接到差分对晶体管的漏极，晶体管的源极在第一个节点连接在一起。 晶体管的主体连接到具有不同于第一节点的电位的第二节点。 在HBM ESD事件发生的情况下，放电可能通过差分晶体管发生，从而导致其中的一个被破坏。 为了降低这种放电的可能性，在优选实施例中，提供开关以在感测到ESD事件时将每个差分晶体管的主体连接到第一节点。 在替代实施例中，当感测到ESD事件时，提供开关以将第一节点连接到第二节点。
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公开(公告)号：US20120091501A1
公开(公告)日：2012-04-19
申请号：US12925277
申请日：2010-10-18
IPC分类号： H01L29/747 , H01L21/332
CPC分类号： H01L29/87 , H01L27/0262 , H01L29/66121
摘要： In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node.
摘要翻译： 在包括连接到高压节点的n +和p +区以及连接到低电压节点的n +和p +区的DIAC类器件中，在连接到低电压节点的n +和p +区之间形成至少两个MOS器件 高压节点，连接到低电压节点的n +和p +区域。
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公开(公告)号：US07808047B1
公开(公告)日：2010-10-05
申请号：US11897915
申请日：2007-08-31
IPC分类号： H01L23/62
CPC分类号： H01L29/6659 , H01L27/0277 , H01L29/1083 , H01L29/1087 , H01L2924/14
摘要： A trigger circuit is provided for a pull-down device by connecting a diode between the I/O pad and the body of the pull-down device. In one embodiment, the pull-down device is formed as a plurality of discrete transistors in a single well. The drain of each transistor is connected through a ballast resistor to the I/O pad; and the source of each transistor is connected through a ballast resistor to ground. The trigger circuit is a diode formed in a different well from that of the transistors. The cathode of the diode is connected to the I/O pad and the anode is connected to the transistor well through a center tap located between the transistors. Preferably, the transistors are NMOS transistors formed in a P-well. Advantageously, the diode is an N+/PLDD diode. Alternatively, the diode is an N+/P diode where the P region is formed by an ESD implant. In other embodiments the diode is formed in the same well as the transistors. In these embodiments, either an N+/PLDD diode or an implanted diode is formed in place of one of the transistors.
摘要翻译： 通过在I / O焊盘和下拉装置的主体之间连接二极管，为下拉装置提供触发电路。 在一个实施例中，下拉装置形成为单个阱中的多个分立晶体管。 每个晶体管的漏极通过镇流电阻连接到I / O焊盘; 并且每个晶体管的源极通过镇流电阻器连接到地。 触发电路是形成在与晶体管不同的阱中的二极管。 二极管的阴极连接到I / O焊盘，阳极通过位于晶体管之间的中心抽头连接到晶体管。 优选地，晶体管是形成在P阱中的NMOS晶体管。 有利地，二极管是N + / PLDD二极管。 或者，二极管是N + / P二极管，其中P区由ESD注入形成。 在其他实施例中，二极管形成在与晶体管相同的阱中。 在这些实施例中，形成N + / PLDD二极管或注入二极管代替晶体管之一。
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公开(公告)号：US07760477B1
公开(公告)日：2010-07-20
申请号：US11868705
申请日：2007-10-08
申请人： Jeffrey T. Watt , Antonio Gallerano
发明人： Jeffrey T. Watt , Antonio Gallerano
CPC分类号： H02H9/046
摘要： A conventional ESD protection circuit connects a diode and main clamp between a pad or node to be protected and ground. To preserve high speed operation while improving charge device model (CDM) performance, the invention also connects between pad and ground a small diode in series with a secondary clamp and a small isolation resistance. The isolation resistance is approximately 20 ohms. The secondary clamp can be as small as 30 nm wide. Parallel diodes on the main clamp can be replaced with an N+/p-substrate (native) diode 290 to further reduce capacitance.
摘要翻译： 传统的ESD保护电路将二极管和主钳夹连接在待保护和接地的焊盘或节点之间。 为了在改善充电装置型号（CDM）性能的同时保持高速运行，本发明还将焊盘与二极管串联连接在一起，并与次级钳位串联并具有较小的隔离电阻。 隔离电阻约为20欧姆。 次钳可以小到30nm宽。 主钳位上的并联二极管可以用N + / p衬底（原生）二极管290代替，以进一步降低电容。
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10.发明授权Method and apparatus for improving triggering uniformity of snapback electrostatic discharge protection devices 有权用于提高闪回静电放电保护装置的触发均匀性的方法和装置公开(公告)号：US08120112B1
公开(公告)日：2012-02-21
申请号：US11904706
申请日：2007-09-28
申请人： Jeffrey T. Watt , Antonio Gallerano
发明人： Jeffrey T. Watt , Antonio Gallerano
IPC分类号： H01L23/58
CPC分类号： H01L27/0277
摘要： An electrostatic discharge (ESD) protection circuit includes a first array of transistors, having source and drain doped with a first type of material, arranged in parallel in a first block, and a second array of transistors, having source and drain doped with the first type of material, arranged in parallel in a second block. The ESD protection circuit also includes an active region between the first and second array of transistors doped with a second type of material that is complementary to the first type of material.
摘要翻译： 静电放电（ESD）保护电路包括：第一晶体管阵列，其具有掺杂有第一类型材料的源极和漏极，并排布置在第一块中;以及第二晶体管阵列，其具有源极和漏极掺杂有第一 材料类型，平行布置在第二块中。 ESD保护电路还包括掺杂有与第一类型材料互补的第二类型材料的第一和第二晶体阵列之间的有源区。
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