公开(公告)号：US09305992B2

公开(公告)日：2016-04-05

申请号：US13161893

申请日：2011-06-16

申请人： Shuxian Chen ,  Jeffrey T. Watt

发明人： Shuxian Chen ,  Jeffrey T. Watt

IPC分类号： H01L49/02 ,  H01L23/522 ,  H01F17/00

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F2017/0046 ,  H01F2017/0073 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inductor may be formed from a conductive path that includes intertwined conductive lines. There may be two, three, or more than three intertwined conductive lines in the conductive path. The conductive lines may be formed from conductive structures in the dielectric stack of an integrated circuit. The dielectric stack may include metal layers that include conductive traces and may include via layers that include vias for interconnecting the traces. The intertwined conductive lines may be formed from the conductive structures in the metal and via layers. In crossover regions, the conductive lines may cross each other without electrically connecting to each other. Vias may be used to couple multiple layers of traces together to reduce line resistance.

摘要翻译： 电感器可以由包括相互缠绕的导线的导电路径形成。 在导电路径中可能有两个，三个或多于三个相互缠绕的导线。 导电线可以由集成电路的电介质堆叠中的导电结构形成。 电介质堆叠可以包括包括导电迹线的金属层，并且可以包括通孔层，其包括用于互连迹线的通孔。 相互缠绕的导线可以由金属和通孔层中的导电结构形成。 在交叉区域中，导线可彼此交叉而不彼此电连接。 通孔可用于将多层迹线耦合在一起以降低线路电阻。

公开(公告)号：US09224685B1

公开(公告)日：2015-12-29

申请号：US13416137

申请日：2012-03-09

申请人： Weiqi Ding ,  Wilson Wong ,  Shuxian Chen ,  Jeffrey T. Watt

发明人： Weiqi Ding ,  Wilson Wong ,  Shuxian Chen ,  Jeffrey T. Watt

IPC分类号： H01L23/522 ,  H01L49/02

CPC分类号： H01L23/5226 ,  H01L23/522 ,  H01L23/5223 ,  H01L23/5225 ,  H01L28/82 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal-oxide-metal (MOM) capacitor structure is disclosed. The MOM capacitor includes a plurality of layers, each layer having a plurality of electrodes. The plurality of electrodes, separated by oxide layers, forms a first plate and a second plate of the MOM capacitor. The plurality of electrodes on each of the layers is coupled to a plurality of electrodes on an adjacent layer through a plurality of vias. A shield layer is coupled to each of the electrodes that forms the second plate of the MOM capacitor on each of the plurality of layers.

摘要翻译： 公开了一种金属氧化物金属（MOM）电容器结构。 MOM电容器包括多个层，每层具有多个电极。 由氧化物层分隔开的多个电极形成MOM电容器的第一板和第二板。 每个层上的多个电极通过多个通孔耦合到相邻层上的多个电极。 屏蔽层耦合到在多个层中的每一层上形成MOM电容器的第二板的每个电极。

公开(公告)号：US08912605B1

公开(公告)日：2014-12-16

申请号：US13538508

申请日：2012-06-29

申请人： Charles Y. Chu ,  Jeffrey T. Watt

发明人： Charles Y. Chu ,  Jeffrey T. Watt

IPC分类号： H01L23/62

CPC分类号： H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-fingered gate transistor formed in a substrate of one conductivity type overlying a well of a second conductivity type. Ohmic contact to the well is made by an implanted region of the second conductivity type that circumscribes the gate transistor. Ohmic contact to the substrate is made by taps located on sides of the gate structure between the gate structure and the well contact. Floating wells are located on opposite sides of the gate structure between the substrate taps and the ends of the gates to isolate these substrate taps and force current flow in the substrate under the gate transistor to be substantially perpendicular to the direction in which the gate fingers extend. This increases the potential difference between these substrate regions and source regions in the gate transistor, thereby aiding the triggering of the parasitic bipolar transistors under adjacent gate fingers into a high current state.

摘要翻译： 形成在覆盖第二导电类型的阱的一种导电类型的衬底中的多指栅极晶体管。 与阱的欧姆接触由限制栅晶体管的第二导电类型的注入区域制成。 通过位于栅极结构和阱接触之间的栅极结构侧面的抽头来形成与衬底的欧姆接触。 浮动阱位于栅极结构的相对侧的栅极结构的两侧之间，以隔离这些衬底抽头并迫使栅极晶体管下方的衬底中的电流大致垂直于栅极指延伸的方向 。 这增加了栅极晶体管中的这些衬底区域和源极区域之间的电势差，从而有助于将相邻栅极指状物处的寄生双极晶体管触发成高电流状态。

公开(公告)号：US08698516B2

公开(公告)日：2014-04-15

申请号：US13214144

申请日：2011-08-19

申请人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

发明人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

IPC分类号： H03K17/16

CPC分类号： H03K19/17784 ,  H03K19/17792

摘要： A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values.

摘要翻译： 现场可编程门阵列（FPGA）包括一组监视器电路，其适于为FPGA中的至少一个电路提供过程，电压和温度的指示，以及控制器，其适于导出所述at的至少一个电路的体偏值的范围 用于至少一个电路的过程，电压和温度的指示的至少一个电路。 FPGA还包括体偏置发生器，其适于向至少一个电路中的至少一个晶体管提供体偏置信号。 体偏置信号具有在体偏值范围内的值。

公开(公告)号：US08643108B2

公开(公告)日：2014-02-04

申请号：US13214102

申请日：2011-08-19

申请人： Irfan Rahim ,  Jeffrey T. Watt ,  Yanzhong Xu ,  Lin-Shih Liu

发明人： Irfan Rahim ,  Jeffrey T. Watt ,  Yanzhong Xu ,  Lin-Shih Liu

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L29/7851 ,  H01L21/761 ,  H01L29/66795

摘要： One embodiment relates to a buffered transistor device. The device includes a buffered vertical fin-shaped structure formed in a semiconductor substrate. The vertical fin-shaped structure includes at least an upper semiconductor layer, a buffer region, and at least part of a well region. The buffer region has a first doping polarity, and the well region has a second doping polarity which is opposite to the first doping polarity. At least one p-n junction that at least partially covers a horizontal cross section of the vertical fin-shaped structure is formed between the buffer and well regions. Other embodiments, aspects, and features are also disclosed.

摘要翻译： 一个实施例涉及缓冲晶体管器件。 该器件包括形成在半导体衬底中的缓冲的垂直鳍状结构。 垂直鳍状结构至少包括上半导体层，缓冲区和阱区​​的至少一部分。 缓冲区具有第一掺杂极性，并且阱区具有与第一掺杂极性相反的第二掺杂极性。 在缓冲区和阱区​​之间形成至少部分覆盖垂直鳍状结构的水平横截面的至少一个p-n结。 还公开了其它实施例，方面和特征。

公开(公告)号：US08619398B1

公开(公告)日：2013-12-31

申请号：US13365579

申请日：2012-02-03

申请人： Antonio Gallerano ,  Charles Y. Chu ,  Jeffrey T. Watt

发明人： Antonio Gallerano ,  Charles Y. Chu ,  Jeffrey T. Watt

IPC分类号： H02H3/22

CPC分类号： H02H3/22

摘要： In a conventional differential output circuit, the output terminals are connected to the drains of a differential pair of transistors and the sources of the transistors are connected together at a first node. The bodies of the transistors are connected to a second node having a potential different from that of the first node. In the event of a HBM ESD event, discharge may take place through the differential transistors, leading to destruction of one of them. To reduce the likelihood of such discharge, in a preferred embodiment, switches are provided to connect the body of each of the differential transistors to the first node when an ESD event is sensed. In an alternative embodiment, a switch is provided to connect the first node to the second node when an ESD event is sensed.

摘要翻译： 在传统的差分输出电路中，输出端连接到差分对晶体管的漏极，晶体管的源极在第一个节点连接在一起。 晶体管的主体连接到具有不同于第一节点的电位的第二节点。 在HBM ESD事件发生的情况下，放电可能通过差分晶体管发生，从而导致其中的一个被破坏。 为了降低这种放电的可能性，在优选实施例中，提供开关以在感测到ESD事件时将每个差分晶体管的主体连接到第一节点。 在替代实施例中，当感测到ESD事件时，提供开关以将第一节点连接到第二节点。

公开(公告)号：US08537523B1

公开(公告)日：2013-09-17

申请号：US12378115

申请日：2009-02-11

申请人： Shuxian Chen ,  Jeffrey T. Watt

发明人： Shuxian Chen ,  Jeffrey T. Watt

IPC分类号： H01G4/005 ,  H01G4/38

CPC分类号： H01L28/86 ,  H01G4/005 ,  H01G4/012 ,  H01G4/33 ,  H01G4/35 ,  H01L23/5223 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal capacitor includes a plurality of interconnect segments. A first plurality of L-shaped fingers is driven to a first voltage level by a first interconnect segment. A second plurality of L-shaped fingers is driven to a second voltage level by a second interconnect segment. Each of the L-shaped fingers from a set of the first plurality of L-shaped fingers is adjacent to at least one of the L-shaped fingers from a set of the second plurality of L-shaped fingers.

公开(公告)号：US08519403B1

公开(公告)日：2013-08-27

申请号：US12931584

申请日：2011-02-04

申请人： Che Ta Hsu ,  Christopher J. Pass ,  Dale Ibbotson ,  Jeffrey T. Watt ,  Yanzhong Xu

发明人： Che Ta Hsu ,  Christopher J. Pass ,  Dale Ibbotson ,  Jeffrey T. Watt ,  Yanzhong Xu

IPC分类号： H01L27/108 ,  H01L29/00 ,  H01L31/036 ,  H01L31/112

CPC分类号： H01L21/823807 ,  H01L21/26586 ,  H01L29/1083

摘要： A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.

摘要翻译： 一种形成亚微米器件的方法包括在包括第一掺杂剂型的多晶硅阱和第二掺杂剂型的栅极的第一区域和包括第二掺杂剂型多晶硅阱的第二区域的第一区域上沉积硬掩模， 第一掺杂剂类型的栅极。 第一个区域上的硬掩模被去除。 执行第一掺杂剂类型的倾斜植入以在第二掺杂剂类型的栅极下形成凹穴。

公开(公告)号：US08482963B1

公开(公告)日：2013-07-09

申请号：US12629831

申请日：2009-12-02

申请人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

发明人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

摘要翻译： 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。

公开(公告)号：US20130043902A1

公开(公告)日：2013-02-21

申请号：US13214144

申请日：2011-08-19

申请人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

发明人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

IPC分类号： H03K19/177

CPC分类号： H03K19/17784 ,  H03K19/17792

摘要： A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values.

摘要翻译： 现场可编程门阵列（FPGA）包括一组监视器电路，其适于为FPGA中的至少一个电路提供过程，电压和温度的指示，以及控制器，其适于导出针对 用于至少一个电路的过程，电压和温度的指示的至少一个电路。 FPGA还包括体偏置发生器，其适于向至少一个电路中的至少一个晶体管提供体偏置信号。 体偏置信号具有在体偏值范围内的值。