发明授权
US07902059B2 Methods of forming void-free layers in openings of semiconductor substrates
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在半导体衬底的开口中形成无空隙层的方法
- 专利标题: Methods of forming void-free layers in openings of semiconductor substrates
- 专利标题(中): 在半导体衬底的开口中形成无空隙层的方法
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申请号: US12608579申请日: 2009-10-29
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公开(公告)号: US07902059B2公开(公告)日: 2011-03-08
- 发明人: Jung-Hwan Kim , Hun-Hyeoung Leam , Jai-Dong Lee , Young-Seok Kim , Young-Sub You , Ki-Su Na , Woong Lee
- 申请人: Jung-Hwan Kim , Hun-Hyeoung Leam , Jai-Dong Lee , Young-Seok Kim , Young-Sub You , Ki-Su Na , Woong Lee
- 申请人地址: KR
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR
- 代理机构: Myers Bigel Sibley & Sajovec
- 优先权: KR2004-0043937 20040615
- 主分类号: H01L21/3205
- IPC分类号: H01L21/3205 ; H01L21/4763
摘要:
In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially fill the opening. A first polysilicon layer is formed by partially etching the first preliminary polysilicon layer until a first void formed in the first preliminary polysilicon layer is exposed. A second polysilicon layer is formed on the first polysilicon layer.
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