发明授权
US07904701B2 Activating a design test mode in a graphics card having multiple execution units to bypass a host cache and transfer test instructions directly to an instruction cache
有权
激活具有多个执行单元的图形卡中的设计测试模式以绕过主机高速缓存并将测试指令直接传送到指令高速缓存
- 专利标题： Activating a design test mode in a graphics card having multiple execution units to bypass a host cache and transfer test instructions directly to an instruction cache
- 专利标题（中）： 激活具有多个执行单元的图形卡中的设计测试模式以绕过主机高速缓存并将测试指令直接传送到指令高速缓存
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申请号： US11759840申请日： 2007-06-07
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公开(公告)号： US07904701B2公开(公告)日： 2011-03-08
- 发明人: Anthony Babella , Allan Wong , Lance Cheney , Brian D. Rauchfuss
- 申请人： Anthony Babella , Allan Wong , Lance Cheney , Brian D. Rauchfuss
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Konrad Raynes & Victor LLP
- 代理商 David W. Victor
- 主分类号： G06F9/00
- IPC分类号： G06F9/00 ; G06F11/00
摘要：
Provided are a method and system for activating a design test mode in a graphics card having multiple execution units. A design test mode is activated in a graphics module comprising multiple execution units coupled to a cache on a bus. The bus is configured to return test instructions from the cache to the execution units in response to a request from one execution unit for the test instructions from the cache in the design test mode. The execution units execute the test instructions during the design test mode. Interrupts are prevented during the design test mode.
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