发明授权
US07920430B2 Integrated circuits and methods for operating the same using a plurality of buffer circuits in an access operation
有权
在访问操作中使用多个缓冲电路来操作该集成电路的集成电路和方法
- 专利标题： Integrated circuits and methods for operating the same using a plurality of buffer circuits in an access operation
- 专利标题（中）： 在访问操作中使用多个缓冲电路来操作该集成电路的集成电路和方法
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申请号： US12166112申请日： 2008-07-01
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公开(公告)号： US07920430B2公开(公告)日： 2011-04-05
- 发明人: Gert Koebernik , Jan Gutsche , Christoph Friederich , Detlev Richter
- 申请人： Gert Koebernik , Jan Gutsche , Christoph Friederich , Detlev Richter
- 申请人地址： DE Munich
- 专利权人： Qimonda AG
- 当前专利权人： Qimonda AG
- 当前专利权人地址： DE Munich
- 代理商 John S. Economou
- 主分类号： G11C7/10
- IPC分类号： G11C7/10
摘要：
In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a plurality of multiple bit information storing memory cells, a plurality of buffer circuits, each buffer circuit being coupled to at least one multiple bit information storing memory cell of the plurality of multiple bit information storing memory cells, and a controller configured to control an access operation to access at least one multiple bit information storing memory cell using the buffer circuit coupled to the at least one multiple bit information storing memory cell to be accessed, and a buffer circuit of at least one other multiple bit information storing memory cell being coupled to at least one other multiple bit information storing memory cell.
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