发明授权
US07943473B2 Minimum cost method for forming high density passive capacitors for replacement of discrete board capacitors using a minimum cost 3D wafer-to-wafer modular integration scheme
有权
使用最小成本的3D晶圆到晶片模块化集成方案形成高密度无源电容器来替代分立板电容器的最低成本方法
- 专利标题： Minimum cost method for forming high density passive capacitors for replacement of discrete board capacitors using a minimum cost 3D wafer-to-wafer modular integration scheme
- 专利标题（中）： 使用最小成本的3D晶圆到晶片模块化集成方案形成高密度无源电容器来替代分立板电容器的最低成本方法
-
申请号： US12352679申请日： 2009-01-13
-
公开(公告)号： US07943473B2公开(公告)日： 2011-05-17
- 发明人: Joseph Paul Ellul , Khanh Tran , Albert Bergemont
- 申请人： Joseph Paul Ellul , Khanh Tran , Albert Bergemont
- 申请人地址： US CA Sunnyvale
- 专利权人： Maxim Integrated Products, Inc.
- 当前专利权人： Maxim Integrated Products, Inc.
- 当前专利权人地址： US CA Sunnyvale
- 代理机构： Blakely Sokoloff Taylor & Zafman LLP
- 主分类号： H01L21/20
- IPC分类号： H01L21/20
摘要：
Passive, high density, 3d IC capacitor stacks and methods that provide the integration of capacitors and integrated circuits in a wafer to wafer bonding process that provides for the integration of capacitors formed on one wafer, alone or with active devices, with one or more integrated circuits on one or more additional wafers that may be stacked in accordance with the process. Wafer to wafer bonding is preferably by thermo-compression, with grinding and chemical mechanical polishing being used to simply aspects of the process of fabrication. Various features and alternate embodiments are disclosed.