A delay synchronization loop type clock signal generating circuit includes: a delay line for delaying a first clock signal by a set delay amount and outputting; a delay time length setting unit for setting a delay time length of the delay line, based on phase difference between a second clock signal output from an output terminal and the first clock signal; a phase relation determining unit for determining whether or not the phase relation of the first clock signal and the second clock signal are in a particular phase relation; and a phase inversion/non-inversion unit for performing phase inversion of the first clock signal on a transmission path including the delay line, at the time of detecting the particular phase relation.