Invention Grant
- Patent Title: Architecture for a message bus
- Patent Title (中): 消息总线架构
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Application No.: US10595538Application Date: 2004-09-08
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Publication No.: US07979766B2Publication Date: 2011-07-12
- Inventor: Manish Sharma , Rakesh Roshan , Manjunath Bittanakurike Narasappa , Bhavani Shanker Arunachalam , Suresh Radhakrishna , William Clement , Joe Jaisingh
- Applicant: Manish Sharma , Rakesh Roshan , Manjunath Bittanakurike Narasappa , Bhavani Shanker Arunachalam , Suresh Radhakrishna , William Clement , Joe Jaisingh
- Applicant Address: IN New Delhi
- Assignee: Centre for Development of Telematics
- Current Assignee: Centre for Development of Telematics
- Current Assignee Address: IN New Delhi
- Agent Narendra Reddy Thappeta
- International Application: PCT/IN2004/000283 WO 20040908
- International Announcement: WO2006/027791 WO 20060316
- Main IPC: G06F13/364
- IPC: G06F13/364

Abstract:
An aspect of the present invention reduces the additional number of signal lines of a bus for control signals by using a set of signal lines to transfer data bits in some durations and to transfer control signals in some other durations. In one embodiment, the same signal lines are used to transfer data in a data transfer phase, and for bus arbitration in a bus arbitration phase. As a result, the total number of signal lines of a bus (bus width) is reduced. According to another aspect of the present invention, an arbitrator block allocates the bus to one of the requesting modules according to an assigned priority and least recently used (LRU) policy.
Public/Granted literature
- US20100115357A1 Novel Architecture for a Message Bus Public/Granted day:2010-05-06
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