公开(公告)号：US07979766B2

公开(公告)日：2011-07-12

申请号：US10595538

申请日：2004-09-08

Applicant: Manish Sharma ,  Rakesh Roshan ,  Manjunath Bittanakurike Narasappa ,  Bhavani Shanker Arunachalam ,  Suresh Radhakrishna ,  William Clement ,  Joe Jaisingh

Inventor： Manish Sharma ,  Rakesh Roshan ,  Manjunath Bittanakurike Narasappa ,  Bhavani Shanker Arunachalam ,  Suresh Radhakrishna ,  William Clement ,  Joe Jaisingh

IPC: G06F13/364

CPC classification number: G06F13/423 ,  G06F11/1443 ,  G06F13/364

Abstract: An aspect of the present invention reduces the additional number of signal lines of a bus for control signals by using a set of signal lines to transfer data bits in some durations and to transfer control signals in some other durations. In one embodiment, the same signal lines are used to transfer data in a data transfer phase, and for bus arbitration in a bus arbitration phase. As a result, the total number of signal lines of a bus (bus width) is reduced. According to another aspect of the present invention, an arbitrator block allocates the bus to one of the requesting modules according to an assigned priority and least recently used (LRU) policy.

Abstract translation: 本发明的一个方面通过使用一组信号线在一些持续时间内传送数据位并且在一些其它持续时间内传送控制信号来减少用于控制信号的总线的附加数量的信号线。 在一个实施例中，相同的信号线用于在数据传送阶段中传送数据，并且用于总线仲裁阶段中的总线仲裁。 结果，总线的信号线总数（总线宽度）减少。 根据本发明的另一方面，仲裁器块根据分配的优先级和最近最少使用（LRU）策略将总线分配给一个请求模块。

公开(公告)号：US20100115357A1

公开(公告)日：2010-05-06

申请号：US10595538

申请日：2004-09-08

Applicant: Manish Sharma ,  Rakesh Roshan ,  Manjunath Bittanakurike Narasappa ,  Bhavani Shanker Arunachlam ,  Suresh Radhakrishna ,  William Clement ,  Joe Jaisinch

Inventor： Manish Sharma ,  Rakesh Roshan ,  Manjunath Bittanakurike Narasappa ,  Bhavani Shanker Arunachlam ,  Suresh Radhakrishna ,  William Clement ,  Joe Jaisinch

IPC: G06F13/00 ,  H04L1/08 ,  G06F11/14

CPC classification number: G06F13/423 ,  G06F11/1443 ,  G06F13/364

Abstract: An aspect of the present invention reduces the additional number of signal lines of a bus (180) for control signals by using a set of signal lines to transfer data bits in some durations and to transfer control signals in some other durations. In one embodiment, the same signal lines are used to transfer data in a data transfer phase, and for bus arbitration (150) in a bus (180) arbitration phase. As a result, the total number of signal lines of a bus (180) (bus width) is reduced. According to another aspect of the present invention, an arbitrator (150) block allocates the bus (180) to one of the requesting modules according to an assigned priority and least recently used (LRU) policy.

Abstract translation: 本发明的一个方面通过使用一组信号线在一些持续时间内传送数据位并在一些其他持续时间内传送控制信号来减少用于控制信号的总线（180）的附加数量的信号线。 在一个实施例中，相同的信号线用于在数据传送阶段中传输数据，并且在总线（180）仲裁阶段中用于总线仲裁（150）。 结果，总线（180）的信号线总数（总线宽度）减小。 根据本发明的另一方面，仲裁器（150）块根据分配的优先级和最近最少使用（LRU）策略将总线（180）分配给一个请求模块。