Invention Grant
US07994553B2 CMOS-based planar type silicon avalanche photo diode using silicon epitaxial layer and method of manufacturing the same
有权
使用硅外延层的CMOS基平面型硅雪崩光电二极管及其制造方法
- Patent Title: CMOS-based planar type silicon avalanche photo diode using silicon epitaxial layer and method of manufacturing the same
- Patent Title (中): 使用硅外延层的CMOS基平面型硅雪崩光电二极管及其制造方法
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Application No.: US12195166Application Date: 2008-08-20
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Publication No.: US07994553B2Publication Date: 2011-08-09
- Inventor: Yong Sun Yoon , Kun Sik Park , Jong Moon Park , Bo Woo Kim , Jin Yeong Kang
- Applicant: Yong Sun Yoon , Kun Sik Park , Jong Moon Park , Bo Woo Kim , Jin Yeong Kang
- Applicant Address: KR Daejeon
- Assignee: Electronics and Telecommunications Research Institute
- Current Assignee: Electronics and Telecommunications Research Institute
- Current Assignee Address: KR Daejeon
- Priority: KR10-2007-0128278 20071211
- Main IPC: H01L31/062
- IPC: H01L31/062

Abstract:
A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes are formed.
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