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公开(公告)号：US08629020B2
公开(公告)日：2014-01-14
申请号：US13228479
申请日：2011-09-09
Applicant: Sang Gi Kim , Jin-Gun Koo , Seong Wook Yoo , Jong-Moon Park , Jin Ho Lee , Kyoung Il Na , Yil Suk Yang , Jongdae Kim
Inventor： Sang Gi Kim , Jin-Gun Koo , Seong Wook Yoo , Jong-Moon Park , Jin Ho Lee , Kyoung Il Na , Yil Suk Yang , Jongdae Kim
IPC: H01L21/336
CPC classification number: H01L29/7813 , H01L21/2255 , H01L29/0634 , H01L29/0653 , H01L29/1095 , H01L29/66727 , H01L29/66734 , H01L29/7811
Abstract: Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer.
Abstract translation: 提供半导体器件及其制造方法。 该方法包括：在第一导电类型的半导体衬底中形成沟槽; 在所述沟槽的侧壁和底表面上形成包含第二导电类型的掺杂剂的沟槽掺杂剂层; 通过将所述沟槽掺杂剂含量层中的掺杂剂扩散到所述半导体衬底中来形成掺杂区域; 并去除含沟槽掺杂剂层。
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公开(公告)号：US20130087884A1
公开(公告)日：2013-04-11
申请号：US13493458
申请日：2012-06-11
Applicant: Hyun-Cheol BAE , Kwang-Seong CHOI , Jong Tae Moon , Jong-Moon PARK
Inventor： Hyun-Cheol BAE , Kwang-Seong CHOI , Jong Tae Moon , Jong-Moon PARK
IPC: H01L27/08
CPC classification number: H01L27/08 , H01L23/147 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/5227 , H01L27/0694 , H01L2924/0002 , H01L2924/19042 , H01L2924/00
Abstract: Disclosed is a silicon interposer that can reduce the entire area of a semiconductor package and increase the degree of integration by forming inductors at a lower part in addition to an upper part of a silicon substrate. The silicon interposer includes a silicon substrate, an upper inductor layer formed at the upper part of the silicon substrate and a lower inductor layer formed at the lower part of the silicon substrate.
Abstract translation: 公开了一种硅插入器，其可以减少半导体封装的整个面积，并且除了硅衬底的上部之外，通过在下部形成电感器来增加集成度。 硅插入器包括硅衬底，形成在硅衬底的上部的上电感器层和形成在硅衬底的下部的下电感层。
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3.发明申请CMOS-BASED PLANAR TYPE SILICON AVALANCHE PHOTO DIODE USING SILICON EPITAXIAL LAYER AND METHOD OF MANUFACTURING THE SAME 有权使用硅外延层的基于CMOS的平面型硅氧化物照相二极管及其制造方法公开(公告)号：US20090146238A1
公开(公告)日：2009-06-11
申请号：US12195166
申请日：2008-08-20
Applicant: Yong Sun Yoon , Kun Sik Park , Jong Moon Park , Bo Woo Kim , Jin Yeong Kang
Inventor： Yong Sun Yoon , Kun Sik Park , Jong Moon Park , Bo Woo Kim , Jin Yeong Kang
IPC: H01L31/103 , H01L31/18
CPC classification number: H01L31/107
Abstract: A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes are formed.
Abstract translation: 使用硅外延层的基于互补金属氧化物半导体（CMOS）的平面型雪崩光电二极管（APD）和制造该APD的方法，所述光电二极管包括：衬底; 在衬底中形成的第一导电类型的阱层; 通过低能离子注入形成在第一导电类型的阱层中的雪崩嵌入结; 形成在雪崩嵌入结的硅外延层; 由所述第一导电类型的阱层的表面的一部分形成在所述雪崩嵌入结中并形成p-n结的与所述第一导电类型相反的第二导电类型的掺杂区域; 分别形成在第二导电类型的掺杂区域上的正极和负极以及从第二导电类型的掺杂区域分离的第一导电类型的阱层; 以及形成在除了形成正极和负极的窗口之外的整个表面上的氧化物层。
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4.发明授权Bipolar junction transistor-based uncooled infrared sensor and manufacturing method thereof 有权双极结晶体管型非制冷红外传感器及其制造方法公开(公告)号：US07855366B2
公开(公告)日：2010-12-21
申请号：US12111830
申请日：2008-04-29
Applicant: Kun Sik Park , Yong Sun Yoon , Bo Woo Kim , Jin Yeong Kang , Jong Moon Park , Seong Wook Yoo
Inventor： Kun Sik Park , Yong Sun Yoon , Bo Woo Kim , Jin Yeong Kang , Jong Moon Park , Seong Wook Yoo
IPC: G01J5/20
CPC classification number: G01J5/20 , H01L21/762 , H01L27/1203
Abstract: A BJT (bipolar junction transistor)-based uncooled IR sensor and a manufacturing method thereof are provided. The BJT-based uncooled IR sensor includes: a substrate; at least one BJT which is formed to be floated apart from the substrate; and a heat absorption layer which is formed on an upper surface of the at least one BJT, wherein the BJT changes an output value according heat absorbed through the heat absorption layer. Accordingly, it is possible to provide a BJT-based uncooled IR sensor capable of being implemented through a CMOS compatible process and obtaining more excellent temperature change detection characteristics.
Abstract translation: 提供了一种基于BJT（双极结型晶体管）的非制冷IR传感器及其制造方法。 基于BJT的非制冷红外传感器包括：基板; 至少一个BJT，其形成为与衬底分开浮动; 以及形成在所述至少一个BJT的上表面上的吸热层，其中所述BJT根据通过所述吸热层吸收的热量来改变输出值。 因此，可以提供能够通过CMOS兼容工艺实现的BJT系非冷却IR传感器，并获得更优异的温度变化检测特性。
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公开(公告)号：US07190432B2
公开(公告)日：2007-03-13
申请号：US11249783
申请日：2005-10-13
Applicant: Sang Gi Kim , Ju Wook Lee , Jong Moon Park , Seong Wook Yoo , Kun Sik Park , Yong Sun Yoon , Yoon Kyu Bae , Byung Won Lim , Jin Gun Koo , Boo Woo Kim
Inventor： Sang Gi Kim , Ju Wook Lee , Jong Moon Park , Seong Wook Yoo , Kun Sik Park , Yong Sun Yoon , Yoon Kyu Bae , Byung Won Lim , Jin Gun Koo , Boo Woo Kim
CPC classification number: G03F7/70425
Abstract: Provided is a wafer exposure apparatus used in a semiconductor device manufacturing process, the exposure apparatus including: a reflective mirror for reflecting light provided from a light source; an optical path changer for changing a path of the light provided from the reflective mirror; first mirrors installed at both sides of the optical path changer to change the path of the light; second mirrors installed at both sides of a material to change the path of the light; and third mirrors installed at both sides of a mask to enter the light reflected by the first mirrors to the mask and to enter the light passed through the mask into the second mirrors, whereby it is possible to continuously expose one surface, both surfaces or a specific surface of a wafer in a state that the wafer is once aligned.
Abstract translation: 提供了一种在半导体器件制造工艺中使用的晶片曝光装置，该曝光装置包括：用于反射从光源提供的光的反射镜; 用于改变从反射镜提供的光的路径的光路改变器; 首先将镜子安装在光路改换器的两侧，以改变光线的路径; 第二个镜子安装在材料的两侧以改变光线的路径; 和第三反射镜，其安装在掩模的两侧，以将由第一反射镜反射的光进入掩模，并将通过掩模的光进入第二反射镜，由此可以连续地将一个表面，两个表面或一个 在晶片一次对准的状态下晶片的比表面。
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Patent Agency Ranking
公开(公告)号：US20060079030A1
公开(公告)日：2006-04-13
申请号：US11179983
申请日：2005-07-12
Applicant: Jong Moon Park , Kun Sik Park , Seong Wook Yoo , Yong Sun Yoon , Sang Gi Kim , Yoon Kyu Bae , Byung Won Lim , Jin Gun Koo , Bo Woo Kim
Inventor： Jong Moon Park , Kun Sik Park , Seong Wook Yoo , Yong Sun Yoon , Sang Gi Kim , Yoon Kyu Bae , Byung Won Lim , Jin Gun Koo , Bo Woo Kim
IPC: H01L21/8232 , H01L21/338
CPC classification number: H01L21/28587
Abstract: Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking layer; exposing a predetermined portion of the second photoresist layer to form a head pattern of the T-type gate, and performing a heat treatment process to generate cross linking at a predetermined region of the second photoresist layer except for the head pattern of the T-type gate; performing an exposure process on an entire surface of the resultant structure, and then removing the exposed portion; and forming a metal layer of a predetermined thickness on an entire surface of the resultant structure, and then removing the first photoresist layer, the blocking layer, the predetermined region of the second photoresist layer in which the cross linking are generated, and the metal layer, whereby it is possible to readily perform a compound semiconductor device manufacturing process, and to reduce manufacturing cost by means of the increase of manufacturing yield and the simplification of manufacturing processes.
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7.发明申请公开(公告)号：US20170196241A1
公开(公告)日：2017-07-13
申请号：US15316181
申请日：2015-06-01
Applicant: Young II KIM , Jong Moon PARK , Egreen Co., Ltd.
Inventor： Young Il KIM , Jong Moon PARK
Abstract: The present invention relates to a method of preparing high-strength coated whole cottonseed for livestock feed, wherein the germination ability of whole cottonseed is removed using high-temperature and high-pressure steam, and the surface of whole cottonseed is coated with gelatinized starch with high viscosity, which is prepared by gelatinizing starch in a preparation process. According the method of the present invention, since the germination ability of whole cottonseed is removed, release of foreign genes into the domestic environment, which may occur when using whole cottonseed for livestock feed, may be fundamentally prevented, and thus the method of the present invention may contribute to protection of domestic plant genetic resources. In addition, the use of gelatinized starch with increased viscosity, which is prepared by gelatinizing starch in a preparation process, may dramatically increase the selection range of coating agents. Furthermore, since coated whole cottonseed can be prepared without a drying process, which consumes a large amount of energy, the method of the present invention may increase economic effect by resolving economic problems, such as high production costs, encountered when preparing whole cottonseed for livestock feed.
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公开(公告)号：US08723292B2
公开(公告)日：2014-05-13
申请号：US13493458
申请日：2012-06-11
Applicant: Hyun-Cheol Bae , Kwang-Seong Choi , Jong Tae Moon , Jong-Moon Park
Inventor： Hyun-Cheol Bae , Kwang-Seong Choi , Jong Tae Moon , Jong-Moon Park
IPC: H01L27/08
CPC classification number: H01L27/08 , H01L23/147 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/5227 , H01L27/0694 , H01L2924/0002 , H01L2924/19042 , H01L2924/00
Abstract: Disclosed is a silicon interposer that can reduce the entire area of a semiconductor package and increase the degree of integration by forming inductors at a lower part in addition to an upper part of a silicon substrate. The silicon interposer includes a silicon substrate, an upper inductor layer formed at the upper part of the silicon substrate and a lower inductor layer formed at the lower part of the silicon substrate.
Abstract translation: 公开了一种硅插入器，其可以减少半导体封装的整个面积，并且除了硅衬底的上部之外，通过在下部形成电感器来增加集成度。 硅插入器包括硅衬底，形成在硅衬底的上部的上电感器层和形成在硅衬底的下部的下电感层。
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公开(公告)号：US07141464B2
公开(公告)日：2006-11-28
申请号：US11179983
申请日：2005-07-12
Applicant: Jong Moon Park , Kun Sik Park , Seong Wook Yoo , Yong Sun Yoon , Sang Gi Kim , Yoon Kyu Bae , Byung Won Lim , Jin Gun Koo , Bo Woo Kim
Inventor： Jong Moon Park , Kun Sik Park , Seong Wook Yoo , Yong Sun Yoon , Sang Gi Kim , Yoon Kyu Bae , Byung Won Lim , Jin Gun Koo , Bo Woo Kim
IPC: H01L21/338
CPC classification number: H01L21/28587
Abstract: Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking layer; exposing a predetermined portion of the second photoresist layer to form a head pattern of the T-type gate, and performing a heat treatment process to generate cross linking at a predetermined region of the second photoresist layer except for the head pattern of the T-type gate; performing an exposure process on an entire surface of the resultant structure, and then removing the exposed portion; and forming a metal layer of a predetermined thickness on an entire surface of the resultant structure, and then removing the first photoresist layer, the blocking layer, the predetermined region of the second photoresist layer in which the cross linking are generated, and the metal layer, whereby it is possible to readily perform a compound semiconductor device manufacturing process, and to reduce manufacturing cost by means of the increase of manufacturing yield and the simplification of manufacturing processes.
Abstract translation: 提供一种制造T型栅极的方法，包括以下步骤：分别在衬底上形成预定厚度的第一光致抗蚀剂层，阻挡层和第二光致抗蚀剂层; 在所述第二光致抗蚀剂层和所述阻挡层上形成T型栅极的主体图案; 暴露第二光致抗蚀剂层的预定部分以形成T型栅极的头部图案，并且进行热处理工艺以在除了T型的头部图案之外的第二光致抗蚀剂层的预定区域处产生交联 门; 在所得结构的整个表面上进行曝光处理，然后去除所述暴露部分; 在所得结构的整个表面上形成预定厚度的金属层，然后去除第一光致抗蚀剂层，阻挡层，产生交联的第二光致抗蚀剂层的预定区域和金属层 ，由此可以容易地进行化合物半导体器件制造工艺，并且通过增加制造成品率和简化制造工艺来降低制造成本。
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10.发明授权
公开(公告)号：US5964629A
公开(公告)日：1999-10-12
申请号：US754804
申请日：1996-11-21
Applicant: Jong Moon Park , Jin Keon Ku , Ki Hong Kim , Yeong Cheol Hyeon , Min Park
Inventor： Jong Moon Park , Jin Keon Ku , Ki Hong Kim , Yeong Cheol Hyeon , Min Park
CPC classification number: H01J9/025
Abstract: To form a silicon tip having an undercut, a photoresist pattern having a vertical profile or a positive profile is formed on a silicon substrate and an under-cuted isotropic etching process is then performed using the photoresist pattern as a mask. First and second insulation films are formed on the silicon tip and the silicon substrate except for the silicon tip. The first insulation film is then separated from the second insulation film.
Abstract translation: 为了形成具有底切的硅尖端，在硅衬底上形成具有垂直轮廓或正轮廓的光致抗蚀剂图案，然后使用光致抗蚀剂图案作为掩模进行下切各向同性蚀刻工艺。 第一和第二绝缘膜形成在除硅尖端之外的硅尖端和硅衬底上。 然后将第一绝缘膜与第二绝缘膜分离。
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