发明授权
- 专利标题: Memory apparatus
- 专利标题(中): 存储设备
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申请号: US12504211申请日: 2009-07-16
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公开(公告)号: US07994562B2公开(公告)日: 2011-08-09
- 发明人: Hajime Nakabayashi , Yasushi Akasaka , Tetsuya Shibata
- 申请人: Hajime Nakabayashi , Yasushi Akasaka , Tetsuya Shibata
- 申请人地址: JP
- 专利权人: Tokyo Electron Limited
- 当前专利权人: Tokyo Electron Limited
- 当前专利权人地址: JP
- 代理机构: Cantor Colburn LLP
- 优先权: JP2008-184786 20080716
- 主分类号: H01L29/04
- IPC分类号: H01L29/04
摘要:
The memory apparatus includes a memory device including a gate insulating layer formed on a silicon substrate by sequentially stacking a tunnel oxide layer, a charge trap layer, and a block oxide layer in this order, on the silicon substrate. In addition, a gate electrode is formed on the gate insulating layer. The block oxide layer is formed by stacking a first block oxide layer and a second block oxide layer, wherein the first block oxide layer is adjacent to the charge trap layer and the second block oxide layer is adjacent to the gate electrode. The second block oxide layer is formed of a dielectric material having higher permittivity than that of the first block oxide layer and having higher electron affinity than that of the first block oxide layer.
公开/授权文献
- US20100013000A1 MEMORY APPARATUS 公开/授权日:2010-01-21