发明授权
- 专利标题: Semiconductor device with dual damascene wirings and method for manufacturing same
- 专利标题(中): 具有双镶嵌布线的半导体器件及其制造方法
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申请号: US11659800申请日: 2005-08-12
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公开(公告)号: US08004087B2公开(公告)日: 2011-08-23
- 发明人: Mari Amano , Munehiro Tada , Naoya Furutake , Yoshihiro Hayashi
- 申请人: Mari Amano , Munehiro Tada , Naoya Furutake , Yoshihiro Hayashi
- 申请人地址: JP Tokyo
- 专利权人: NEC Corporation
- 当前专利权人: NEC Corporation
- 当前专利权人地址: JP Tokyo
- 代理机构: McGinn IP Law Group, PLLC
- 优先权: JP2004-235133 20040812
- 国际申请: PCT/JP2005/014855 WO 20050812
- 国际公布: WO2006/016678 WO 20060216
- 主分类号: H01L21/28
- IPC分类号: H01L21/28 ; H01L21/4763
摘要:
A multilayered wiring is formed in a prescribed area in an insulating film that is formed on a semiconductor substrate. Dual damascene wiring that is positioned on at least one layer of the multilayered wiring is composed of an alloy having copper as a principal component. The concentration of at least one metallic element contained in the alloy as an added component in vias of the dual damascene wiring is determined according to the differences in the width of the wiring of an upper layer where the vias are connected. Specifically, a larger wiring width in the upper layer corresponds to a higher concentration of at least one metallic element within the connected vias. Accordingly, increases in the resistance of the wiring are minimized, the incidence of stress-induced voids is reduced, and reliability can be improved.
公开/授权文献
- US20090026622A1 Semiconductor Device and Method for Manufacturing Same 公开/授权日:2009-01-29