公开(公告)号：US20110266678A1

公开(公告)日：2011-11-03

申请号：US13067960

申请日：2011-07-11

申请人： Mari Amano ,  Munehiro Tada ,  Naoya Furutake ,  Yoshihiro Hayashi

发明人： Mari Amano ,  Munehiro Tada ,  Naoya Furutake ,  Yoshihiro Hayashi

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, and a multilayered wiring formed in a prescribed area within the insulating film. The multilayered wiring includes a dual damascene wiring positioned on at least one layer of the multilayered wiring. The dual damascene wiring includes an alloy having copper as a principal component. A concentration of at least one metallic element contained as an added component of the alloy in a via connected to the dual damascene wiring is 10% or more higher in a via connected to a wiring whose width exceeds by five or more times a diameter of the via than that in another via connected to another wiring of a smallest width in a same upper wiring layer of the multilayered wiring.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底上的绝缘膜，以及形成在绝缘膜内的规定区域中的多层布线。 多层布线包括位于多层布线的至少一层上的双镶嵌布线。 双镶嵌线包括以铜为主要成分的合金。 在连接到双镶嵌布线的通孔中作为合金的添加成分含有的至少一种金属元素的浓度在连接到宽度超过五倍或更多倍的布线的通孔中为10％以上 通过连接到多层布线的同一上布线层中的最小宽度的另一布线的通孔。

公开(公告)号：US08198730B2

公开(公告)日：2012-06-12

申请号：US12522814

申请日：2008-01-08

申请人： Masayoshi Tagami ,  Yoshihiro Hayashi ,  Munehiro Tada ,  Takahiro Onodera ,  Naoya Furutake ,  Makoto Ueki ,  Mari Amano

发明人： Masayoshi Tagami ,  Yoshihiro Hayashi ,  Munehiro Tada ,  Takahiro Onodera ,  Naoya Furutake ,  Makoto Ueki ,  Mari Amano

IPC分类号： H01L23/52

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/7684 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a multilayer interconnection including a copper interconnection film formed in a predetermined area within an insulating film, a liner film, and a high-melting-point metal film. The copper interconnection film is polycrystalline, and crystal grains occupying 40% or more of an area of a unit interconnection surface among crystal grains forming the polycrystal are oriented to (111) in a substrate thickness direction. The copper interconnection film has crystal conformity with the noble metal liner film. In a case where the high-melting-point metal film is formed of Ti and the noble metal liner film is a Ru film, the high-melting-point metal of Ti dissolves into Ru in a solid state to form the noble metal liner. Thus, a copper interconnection is formed with both of Cu diffusion barrier characteristics and Cu crystal conformity.

摘要翻译： 半导体器件具有包括形成在绝缘膜内的预定区域中的铜互连膜，衬里膜和高熔点金属膜的多层互连。 铜互连膜是多晶的，并且占据形成多晶体的晶粒中的单位互连表面的面积的40％以上的晶粒在基板厚度方向上取向为（111）。 铜互连膜与贵金属衬垫膜具有晶体一致性。 在高熔点金属膜由Ti形成并且贵金属衬垫膜是Ru膜的情况下，Ti的高熔点金属以固态溶解到Ru中以形成贵金属衬垫。 因此，铜互连形成为Cu扩散阻挡特性和Cu晶体一致性。

公开(公告)号：US08916466B2

公开(公告)日：2014-12-23

申请号：US13067960

申请日：2011-07-11

申请人： Mari Amano ,  Munehiro Tada ,  Naoya Furutake ,  Yoshihiro Hayashi

发明人： Mari Amano ,  Munehiro Tada ,  Naoya Furutake ,  Yoshihiro Hayashi

IPC分类号： H01L23/485 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, and a multilayered wiring formed in a prescribed area within the insulating film. The multilayered wiring includes a dual damascene wiring positioned on at least one layer of the multilayered wiring. The dual damascene wiring includes an alloy having copper as a principal component. A concentration of at least one metallic element contained as an added component of the alloy in a via connected to the dual damascene wiring is 10% or more higher in a via connected to a wiring whose width exceeds by five or more times a diameter of the via than that in another via connected to another wiring of a smallest width in a same upper wiring layer of the multilayered wiring.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底上的绝缘膜，以及形成在绝缘膜内的规定区域中的多层布线。 多层布线包括位于多层布线的至少一层上的双镶嵌布线。 双镶嵌线包括以铜为主要成分的合金。 在连接到双镶嵌布线的通孔中作为合金的添加成分含有的至少一种金属元素的浓度在连接到宽度超过五倍或更多倍的布线的通孔中为10％以上 通过连接到多层布线的同一上布线层中的最小宽度的另一布线的通孔。

公开(公告)号：US20100193953A1

公开(公告)日：2010-08-05

申请号：US11993285

申请日：2006-05-23

申请人： Mari Amano ,  Munehiro Tada ,  Naoya Furutake ,  Yoshihiro Hayashi

发明人： Mari Amano ,  Munehiro Tada ,  Naoya Furutake ,  Yoshihiro Hayashi

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76877 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76841 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A trench is formed in an insulation film formed on top of a semiconductor substrate, and a barrier metal film is formed on the surface of the trench. After a copper or copper alloy film is formed on the barrier metal film, an oxygen absorption film in which a standard energy of formation of an oxidation reaction in a range from room temperature to 400° C. is negative, and in which an absolute value of the standard energy of formation is larger than that of the barrier metal film is formed, and the assembly is heated in a temperature range of 200 to 400° C. A semiconductor device can thereby be provided that has highly reliable wiring, in which the adhesion to the barrier metal film in the copper interface is enhanced, copper diffusion in the interface is suppressed, and electromigration and stress migration are prevented.

摘要翻译： 在形成于半导体衬底顶部的绝缘膜上形成沟槽，并且在沟槽的表面上形成阻挡金属膜。 在阻挡金属膜上形成铜或铜合金膜之后，在室温至400℃的范围内形成氧化反应的标准能量为负的氧吸收膜，其中绝对值 的标准形成能量大于形成阻挡金属膜的能量，并且组件在200至400℃的温度范围内被加热。由此可以提供具有高可靠性布线的半导体器件，其中 增加了铜界面对阻挡金属膜的附着力，抑制了界面的铜扩散，防止了电迁移和应力迁移。

公开(公告)号：US07867906B2

公开(公告)日：2011-01-11

申请号：US11993285

申请日：2006-05-23

申请人： Mari Amano ,  Munehiro Tada ,  Naoya Furutake ,  Yoshihiro Hayashi

发明人： Mari Amano ,  Munehiro Tada ,  Naoya Furutake ,  Yoshihiro Hayashi

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76877 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76841 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A trench is formed in an insulation film formed on top of a semiconductor substrate, and a barrier metal film is formed on the surface of the trench. After a copper or copper alloy film is formed on the barrier metal film, an oxygen absorption film in which a standard energy of formation of an oxidation reaction in a range from room temperature to 400° C. is negative, and in which an absolute value of the standard energy of formation is larger than that of the barrier metal film is formed, and the assembly is heated in a temperature range of 200 to 400° C. A semiconductor device can thereby be provided that has highly reliable wiring, in which the adhesion to the barrier metal film in the copper interface is enhanced, copper diffusion in the interface is suppressed, and electromigration and stress migration are prevented.

摘要翻译： 在形成于半导体衬底顶部的绝缘膜上形成沟槽，并且在沟槽的表面上形成阻挡金属膜。 在阻挡金属膜上形成铜或铜合金膜之后，在室温至400℃的范围内形成氧化反应的标准能量为负的氧吸收膜，其中绝对值 的标准形成能量大于形成阻挡金属膜的能量，并且组件在200至400℃的温度范围内被加热。由此可以提供具有高可靠性布线的半导体器件，其中 增加了铜界面对阻挡金属膜的附着力，抑制了界面的铜扩散，防止了电迁移和应力迁移。

公开(公告)号：US20100096756A1

公开(公告)日：2010-04-22

申请号：US12522814

申请日：2008-01-08

申请人： Masayoshi Tagami ,  Yoshihiro Hayashi ,  Munehiro Tada ,  Takahiro Onodera ,  Naoya Furutake ,  Makoto Ueki ,  Mari Amano

发明人： Masayoshi Tagami ,  Yoshihiro Hayashi ,  Munehiro Tada ,  Takahiro Onodera ,  Naoya Furutake ,  Makoto Ueki ,  Mari Amano

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/7684 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a multilayer interconnection including a copper interconnection film formed in a predetermined area within an insulating film, a liner film, and a high-melting-point metal film. The copper interconnection film is polycrystalline, and crystal grains occupying 40% or more of an area of a unit interconnection surface among crystal grains forming the polycrystal are oriented to (111) in a substrate thickness direction. The copper interconnection film has crystal conformity with the noble metal liner film. In a case where the high-melting-point metal film is formed of Ti and the noble metal liner film is a Ru film, the high-melting-point metal of Ti dissolves into Ru in a solid state to form the noble metal liner. Thus, a copper interconnection is formed with both of Cu diffusion barrier characteristics and Cu crystal conformity.

摘要翻译： 半导体器件具有包括形成在绝缘膜内的预定区域中的铜互连膜，衬里膜和高熔点金属膜的多层互连。 铜互连膜是多晶的，并且占据形成多晶体的晶粒中的单位互连表面的面积的40％以上的晶粒在基板厚度方向上取向为（111）。 铜互连膜与贵金属衬垫膜具有晶体一致性。 在高熔点金属膜由Ti形成并且贵金属衬垫膜是Ru膜的情况下，Ti的高熔点金属以固态溶解到Ru中以形成贵金属衬垫。 因此，铜互连形成为Cu扩散阻挡特性和Cu晶体一致性。

公开(公告)号：US08174122B2

公开(公告)日：2012-05-08

申请号：US12956333

申请日：2010-11-30

申请人： Mari Amano ,  Munehiro Tada ,  Naoya Furutake ,  Yoshihiro Hayashi

发明人： Mari Amano ,  Munehiro Tada ,  Naoya Furutake ,  Yoshihiro Hayashi

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76877 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76841 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A trench is formed in an insulation film formed on top of a semiconductor substrate, and a barrier metal film is formed on the surface of the trench. After a copper or copper alloy film is formed on the barrier metal film, an oxygen absorption film in which a standard energy of formation of an oxidation reaction in a range from room temperature to 400° C. is negative, and in which an absolute value of the standard energy of formation is larger than that of the barrier metal film is formed, and the assembly is heated in a temperature range of 200 to 400° C. A semiconductor device can thereby be provided that has highly reliable wiring, in which the adhesion to the barrier metal film in the copper interface is enhanced, copper diffusion in the interface is suppressed, and electromigration and stress migration are prevented.

摘要翻译： 在形成于半导体衬底顶部的绝缘膜上形成沟槽，并且在沟槽的表面上形成阻挡金属膜。 在阻挡金属膜上形成铜或铜合金膜之后，在室温至400℃的范围内形成氧化反应的标准能量为负的氧吸收膜，其中绝对值 的标准形成能量大于形成阻挡金属膜的能量，并且组件在200至400℃的温度范围内被加热。由此可以提供具有高可靠性布线的半导体器件，其中 增加了铜界面对阻挡金属膜的附着力，抑制了界面的铜扩散，防止了电迁移和应力迁移。

公开(公告)号：US08004087B2

公开(公告)日：2011-08-23

申请号：US11659800

申请日：2005-08-12

申请人： Mari Amano ,  Munehiro Tada ,  Naoya Furutake ,  Yoshihiro Hayashi

发明人： Mari Amano ,  Munehiro Tada ,  Naoya Furutake ,  Yoshihiro Hayashi

IPC分类号： H01L21/28 ,  H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multilayered wiring is formed in a prescribed area in an insulating film that is formed on a semiconductor substrate. Dual damascene wiring that is positioned on at least one layer of the multilayered wiring is composed of an alloy having copper as a principal component. The concentration of at least one metallic element contained in the alloy as an added component in vias of the dual damascene wiring is determined according to the differences in the width of the wiring of an upper layer where the vias are connected. Specifically, a larger wiring width in the upper layer corresponds to a higher concentration of at least one metallic element within the connected vias. Accordingly, increases in the resistance of the wiring are minimized, the incidence of stress-induced voids is reduced, and reliability can be improved.

摘要翻译： 在形成在半导体衬底上的绝缘膜中的规定区域中形成多层布线。 位于至少一层多层布线上的双镶嵌布线由以铜为主要成分的合金构成。 根据连接有通孔的上层的布线的宽度的差异，确定合金中包含的至少一种金属元素作为双重镶嵌布线的通孔中的添加成分的浓度。 具体地说，上层中较大的布线宽度对应于连接的通孔内的至少一种金属元件的较高浓度。 因此，布线的电阻的增加被最小化，应力引起的空隙的发生率降低，可提高可靠性。

公开(公告)号：US20090026622A1

公开(公告)日：2009-01-29

申请号：US11659800

申请日：2005-08-12

申请人： Mari Amano ,  Munehiro Tada ,  Naoya Furutake ,  Yoshihiro Hayashi

发明人： Mari Amano ,  Munehiro Tada ,  Naoya Furutake ,  Yoshihiro Hayashi

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multilayered wiring is formed in a prescribed area in an insulating film that is formed on a semiconductor substrate. Dual damascene wiring that is positioned on at least one layer of the multilayered wiring is composed of an alloy having copper as a principal component. The concentration of at least one metallic element contained in the alloy as an added component in vias of the dual damascene wiring is determined according to the differences in the width of the wiring of an upper layer where the vias are connected. Specifically, a larger wiring width in the upper layer corresponds to a higher concentration of at least one metallic element within the connected vias. Accordingly, increases in the resistance of the wiring are minimized, the incidence of stress-induced voids is reduced, and reliability can be improved.

摘要翻译： 在形成在半导体衬底上的绝缘膜中的规定区域中形成多层布线。 位于至少一层多层布线上的双镶嵌布线由以铜为主要成分的合金构成。 根据连接有通孔的上层的布线的宽度的差异，确定合金中包含的至少一种金属元素作为双重镶嵌布线的通孔中的添加成分的浓度。 具体地说，上层中较大的布线宽度对应于连接的通孔内的至少一种金属元件的较高浓度。 因此，布线的电阻的增加被最小化，应力引起的空隙的发生率降低，可提高可靠性。

公开(公告)号：US20100219512A1

公开(公告)日：2010-09-02

申请号：US11991745

申请日：2006-09-08

申请人： Munehiro Tada ,  Naoya Furutake ,  Tsuneo Takeuchi ,  Yoshihiro Hayashi

发明人： Munehiro Tada ,  Naoya Furutake ,  Tsuneo Takeuchi ,  Yoshihiro Hayashi

IPC分类号： H01L23/29 ,  H01L21/47

CPC分类号： H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/31695 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1036 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming porous insulating film using cyclic siloxane raw material monomer is provided, which method suppresses detachment of hydrocarbon and is able to form a low-density film.In a method where at least cyclic organosiloxane raw material 101 is supplied to a reaction chamber and an insulating film is formed by plasma vapor deposition method, above-mentioned problem is solved by a method for a forming porous insulating film using the mixed gas of a cyclic organosiloxane raw material 101 and a compound raw material 103 including a part of chemical structure comprising the cyclic organosiloxane raw material 101. The compound raw material 103 is preferably a compound including a part of side chain of the cyclic organosiloxane raw material 101.

摘要翻译： 提供了使用环状硅氧烷原料单体形成多孔绝缘膜的方法，该方法抑制烃的分离并能够形成低密度膜。 在通过等离子体气相沉积法将至少环状有机硅氧烷原料101供给到反应室并形成绝缘膜的方法中，上述问题通过使用以下的混合气体形成多孔绝缘膜的方法来解决： 环状有机硅氧烷原料101和包含环状有机硅氧烷原料101的化学结构的一部分的复合原料103.化合物原料103优选为包含环状有机硅氧烷原料101的侧链的一部分的化合物。