发明授权
- 专利标题： Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers
- 专利标题（中）： 在多个指令定序器上监视基于指令集的线程执行的机制
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申请号： US11151809申请日： 2005-06-13
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公开(公告)号： US08010969B2公开(公告)日： 2011-08-30
- 发明人: Richard A. Hankins , Gautham N. Chinya , Hong Wang , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Trung A. Diep , Xiang Zou , Baiju V. Patel , Paul M. Petersen , Sanjiv M. Shah , Ryan N. Rakvic , Prashant Sethi
- 申请人： Richard A. Hankins , Gautham N. Chinya , Hong Wang , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Trung A. Diep , Xiang Zou , Baiju V. Patel , Paul M. Petersen , Sanjiv M. Shah , Ryan N. Rakvic , Prashant Sethi
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号： G06F3/00
- IPC分类号： G06F3/00 ; G06F9/46 ; G06F7/38
摘要：
A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.