发明授权
US08011090B2 Method for forming and planarizing adjacent regions of an integrated circuit 有权
用于形成和平面化集成电路的相邻区域的方法

Method for forming and planarizing adjacent regions of an integrated circuit
摘要:
Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
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