发明授权
US08011090B2 Method for forming and planarizing adjacent regions of an integrated circuit
有权
用于形成和平面化集成电路的相邻区域的方法
- 专利标题: Method for forming and planarizing adjacent regions of an integrated circuit
- 专利标题(中): 用于形成和平面化集成电路的相邻区域的方法
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申请号: US12123021申请日: 2008-05-19
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公开(公告)号: US08011090B2公开(公告)日: 2011-09-06
- 发明人: Mirzafer Abatchev , David Wells , Baosuo Zhou , Krupakar M. Subramanian
- 申请人: Mirzafer Abatchev , David Wells , Baosuo Zhou , Krupakar M. Subramanian
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 代理机构: Knobbe, Martens, Olson & Bear LLP
- 主分类号: H05K3/02
- IPC分类号: H05K3/02 ; H05K3/10
摘要:
Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
公开/授权文献
- US20080261349A1 PROTECTIVE COATING FOR PLANARIZATION 公开/授权日:2008-10-23
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