发明授权
- 专利标题： Segmented scan paths with cache bit memory inputs
- 专利标题（中）： 具有缓存位存储器输入的分段扫描路径
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申请号： US12204267申请日： 2008-09-04
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公开(公告)号： US08015464B2公开(公告)日： 2011-09-06
- 发明人: Lee D. Whetsel , Joel J. Graber
- 申请人： Lee D. Whetsel , Joel J. Graber
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Lawrence J. Bassuk; W. James Brady; Frederick J. Telecky, Jr.
- 主分类号： G01R31/28
- IPC分类号： G01R31/28
摘要：
Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.
公开/授权文献
- US20080320351A1 LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS 公开/授权日：2008-12-25