发明授权
US08017997B2 Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via 有权
垂直金属绝缘体金属(MIM)电容器,采用栅极叠层,栅极隔离和接触通孔

Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via
摘要:
A semiconductor structure including a vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance.
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