Invention Grant
- Patent Title: Semiconductor memory device comprising a plurality of static memory cells
- Patent Title (中): 半导体存储器件包括多个静态存储单元
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Application No.: US12909465Application Date: 2010-10-21
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Publication No.: US08018785B2Publication Date: 2011-09-13
- Inventor: Makoto Yabuuchi , Koji Nii
- Applicant: Makoto Yabuuchi , Koji Nii
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: McDermott Will & Emery LLP
- Priority: JP2006-218514 20060810; JP2007-125798 20070510
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.
Public/Granted literature
- US20110032750A1 SEMICONDUCTOR MEMORY DEVICE COMPRISING A PLURALITY OF STATIC MEMORY CELLS Public/Granted day:2011-02-10
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