发明授权
- 专利标题: Method characterizing materials for a trench isolation structure having low trench parasitic capacitance
- 专利标题(中): 用于具有低沟槽寄生电容的沟槽隔离结构的方法表征材料
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申请号: US12574426申请日: 2009-10-06
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公开(公告)号: US08021955B1公开(公告)日: 2011-09-20
- 发明人: Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
- 申请人: Venkatesh P. Gopinath , Arvind Kamath , Mohammad R. Mirabedini , Ming-Yi Lee
- 申请人地址: US CA Milpitas
- 专利权人: LSI Logic Corporation
- 当前专利权人: LSI Logic Corporation
- 当前专利权人地址: US CA Milpitas
- 代理机构: Beyer Law Group LLP
- 主分类号: H01L21/76
- IPC分类号: H01L21/76
摘要:
Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A range of effective dielectric constants that correspond to the thicknesses the lower and upper dielectric materials are selected. A range of thicknesses for each of the lower and upper dielectric layers are determined from a range of acceptable dielectric constants using information indicating an effective dielectric constant corresponding to thicknesses of the materials for both the lower upper dielectric layers, enabling the formation of the multi-layer isolation structure.
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