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1.发明授权Strained-silicon for CMOS device using amorphous silicon deposition or silicon epitaxial growth 有权应变硅，用于使用非晶硅沉积或硅外延生长的CMOS器件公开(公告)号：US07429749B2
公开(公告)日：2008-09-30
申请号：US10455489
申请日：2003-06-04
IPC分类号： H01L29/04
CPC分类号： H01L29/78 , H01L21/26506 , H01L29/1054
摘要： An integrated circuit (IC) includes a strained-silicon layer formed by deposition of amorphous silicon onto either a region of a semiconductor layer that has been implanted with ions to create a larger spacing between atoms in a crystalline lattice of the semiconductor layer or a silicon-ion layer that has been epitaxially grown on the semiconductor layer to have an increased spacing between atoms in the silicon-ion layer. Alternatively, the IC includes a strained-silicon layer formed by silicon epitaxial growth onto the region of the semiconductor layer that has been implanted with ions. The IC also preferably includes a CMOS device that preferably, but not necessarily, incorporates sub-0.1 micron technology. The implanted ions may preferably be heavy ions, such as germanium ions, antimony ions or others. Ion implantation may be done with a single implantation process, as well as with multiple implantation processes.
摘要翻译： 集成电路（IC）包括通过将非晶硅沉积在已经注入离子的半导体层的区域上形成的应变硅层，以在半导体层的晶格中形成较大的原子之间或硅 已经在半导体层上外延生长以在硅离子层中的原子之间具有增加的间隔。 或者，IC包括通过硅外延生长形成在已经注入离子的半导体层的区域上的应变硅层。 IC还优选地包括优选但不一定包含次0.1微米技术的CMOS器件。 注入的离子可以优选为重离子，例如锗离子，锑离子等。 离子注入可以通过单个注入工艺以及多次注入工艺完成。
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2.发明授权Method characterizing materials for a trench isolation structure having low trench parasitic capacitance 有权用于具有低沟槽寄生电容的沟槽隔离结构的方法表征材料公开(公告)号：US08021955B1
公开(公告)日：2011-09-20
申请号：US12574426
申请日：2009-10-06
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A range of effective dielectric constants that correspond to the thicknesses the lower and upper dielectric materials are selected. A range of thicknesses for each of the lower and upper dielectric layers are determined from a range of acceptable dielectric constants using information indicating an effective dielectric constant corresponding to thicknesses of the materials for both the lower upper dielectric layers, enabling the formation of the multi-layer isolation structure.
摘要翻译： 提供了用于在集成电路基板上形成多层隔离结构的方法和组合物。 工艺可以包括为下电介质层选择下电介质材料，并选择用于上电介质层的上电介质材料。 选择对应于下部和上部介电材料的厚度的一系列有效介电常数。 下介电层和上电介质层中的每一个的厚度范围由可接受的介电常数的范围决定，使用表示与下部上部电介质层的材料的厚度对应的有效介电常数的信息，能够形成多层电介质层， 层隔离结构。
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3.发明授权Apparatus and method of manufacture for integrated circuit and CMOS device including epitaxially grown dielectric on silicon carbide 有权用于集成电路和CMOS器件的装置和方法，包括在碳化硅上的外延生长的电介质公开(公告)号：US07138292B2
公开(公告)日：2006-11-21
申请号：US10659134
申请日：2003-09-10
IPC分类号： H01L21/00
CPC分类号： H01L21/823857 , H01L21/049 , H01L21/28017 , H01L21/2807 , H01L21/28194 , H01L21/3147 , H01L21/3148 , H01L21/823807 , H01L29/1054 , H01L29/4966 , H01L29/51
摘要： An integrated circuit, or portion thereof, such as a CMOS device, includes an epitaxially grown dielectric on a silicon carbide base. The epitaxially grown dielectric forms a gate dielectric and the silicon carbide base serves as a channel region for the CMOS device. In various embodiments, the epitaxially grown dielectric may be a crystalline carbon or carbon-containing film.
摘要翻译： 诸如CMOS器件的集成电路或其一部分包括在碳化硅基底上的外延生长的电介质。 外延生长的电介质形成栅极电介质，并且碳化硅基底用作CMOS器件的沟道区。 在各种实施方案中，外延生长的电介质可以是结晶碳或含碳膜。
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4.发明授权Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance 有权制造具有低沟槽寄生电容的浅沟槽隔离结构的方法公开(公告)号：US07001823B1
公开(公告)日：2006-02-21
申请号：US09991202
申请日：2001-11-14
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.
摘要翻译： 提供了用于在集成电路基板上形成隔离结构的方法和组合物。 首先，在集成电路基板中蚀刻沟槽。 然后在沟槽中形成下介电层，使得下电介质层至少部分地填充沟槽。 然后在下介电层上形成上电介质层以产生隔离结构，上电介质层和下电介质层一起具有小于二氧化硅的有效介电常数，从而实现与隔离结构相关联的电容 要减少
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公开(公告)号：US06989331B2
公开(公告)日：2006-01-24
申请号：US10615558
申请日：2003-07-08
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/31116
摘要： A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.
摘要翻译： 从形成在下层上的图案化层去除硬掩模层的方法，其中使用蚀刻剂去除硬掩模层，当底层在通常需要的时间长时间暴露于蚀刻剂时不利地蚀刻下面的层 以去除硬掩模层，而不会有害地蚀刻下面的层。 修改硬掩模层，使得蚀刻剂以比蚀刻剂蚀刻下层的蚀刻剂快得多的速率蚀刻硬掩模层。 图案化硬掩模层。 蚀刻图案层以暴露下层的部分。 硬掩模层和下层的暴露部分用蚀刻剂蚀刻，其中蚀刻剂以比蚀刻剂蚀刻下层的速率快得多的速度蚀刻硬掩模层，这是因为硬的 掩模层。
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公开(公告)号：US06930362B1
公开(公告)日：2005-08-16
申请号：US10698167
申请日：2003-10-30
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/76 , H01L29/78
CPC分类号： H01L29/6656 , H01L21/265 , H01L21/28035 , H01L29/4925 , H01L29/78
摘要： A calcium doped polysilicon gate electrodes for PMOS containing semiconductor devices. The calcium doped PMOS gate electrodes reduce migration of the boron dopant out of the gate electrode, through the gate dielectric and into the substrate thereby reducing the boron penetration problem increasingly encountered with smaller device size regimes and their thinner gate dielectrics. Calcium doping of the gate electrode may be achieved by a variety of techniques. It is further believed that the calcium doping may improve the boron dopant activation in the gate electrode, thereby further improving performance.
摘要翻译： 用于含PMOS半导体器件的掺杂钙的多晶硅栅电极。 掺杂钙的PMOS栅电极减少了硼掺杂剂离开栅极电极的迁移，通过栅极电介质并进入衬底中，从而减小了越来越多的器件尺寸状态和其更薄的栅极电介质越来越多地遇到的硼渗透问题。 栅电极的钙掺杂可以通过各种技术来实现。 进一步认为钙掺杂可以改善栅电极中的硼掺杂剂活化，从而进一步提高性能。
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7.发明授权公开(公告)号：US07619294B1
公开(公告)日：2009-11-17
申请号：US11262173
申请日：2005-10-28
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.
摘要翻译： 提供了用于在集成电路基板上形成隔离结构的方法和组合物。 首先，在集成电路基板中蚀刻沟槽。 然后在沟槽中形成下介电层，使得下电介质层至少部分地填充沟槽。 然后在下介电层上形成上电介质层以产生隔离结构，上电介质层和下电介质层一起具有小于二氧化硅的有效介电常数，从而实现与隔离结构相关联的电容 要减少
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8.发明授权Apparatus and method of manufacture for integrated circuit and CMOS device including epitaxially grown dielectric on silicon carbide 有权用于集成电路和CMOS器件的装置和方法，包括在碳化硅上的外延生长的电介质公开(公告)号：US07408227B2
公开(公告)日：2008-08-05
申请号：US11524107
申请日：2006-09-20
IPC分类号： H01L31/0312
CPC分类号： H01L21/823857 , H01L21/049 , H01L21/28017 , H01L21/2807 , H01L21/28194 , H01L21/3147 , H01L21/3148 , H01L21/823807 , H01L29/1054 , H01L29/4966 , H01L29/51
摘要： An integrated circuit, or portion thereof, such as a CMOS device, includes an epitaxially grown dielectric on a silicon carbide base. The epitaxially grown dielectric forms a gate dielectric and the silicon carbide base serves as a channel region for the CMOS device. In various embodiments, the epitaxially grown dielectric may be a crystalline carbon or carbon-containing film.
摘要翻译： 诸如CMOS器件的集成电路或其一部分包括在碳化硅基底上的外延生长的电介质。 外延生长的电介质形成栅极电介质，并且碳化硅基底用作CMOS器件的沟道区。 在各种实施方案中，外延生长的电介质可以是结晶碳或含碳膜。
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公开(公告)号：US07129516B2
公开(公告)日：2006-10-31
申请号：US11098290
申请日：2005-04-04
IPC分类号： H01L29/06 , H01L31/0328
CPC分类号： H01L21/823864 , H01L21/26506 , H01L21/26526 , H01L21/823807 , H01L29/1054
摘要： An integrated circuit (IC) includes a CMOS device formed above a semiconductor substrate having ions therein that are implanted in the semiconductor substrate by an ion recoil procedure. The IC preferably, but not necessarily, incorporates sub-0.1 micron technology in the CMOS device. The implanted ions may preferably be germanium ions. A strained-silicon layer is preferably, but not necessarily, formed above the ion-implanted layer of the semiconductor substrate. The strained-silicon layer may be formed by a silicon epitaxial growth on the ion-implanted layer or by causing the ions to recoil into the semiconductor substrate with such energy that a region of the semiconductor substrate in the vicinity of the surface thereof is left substantially free of the ions, thereby forming a strained-silicon layer in the substantially ion-free region.
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10.发明授权公开(公告)号：US06982229B2
公开(公告)日：2006-01-03
申请号：US10418375
申请日：2003-04-18
IPC分类号： H01L23/48
CPC分类号： H01L21/823864 , H01L21/26506 , H01L21/26526 , H01L21/823807 , H01L29/1054
摘要： An integrated circuit (IC) includes a CMOS device formed above a semiconductor substrate having ions therein that are implanted in the semiconductor substrate by an ion recoil procedure. The IC preferably, but not necessarily, incorporates sub-0.1 micron technology in the CMOS device. The implanted ions may preferably be germanium ions. A strained-silicon layer is preferably, but not necessarily, formed above the ion-implanted layer of the semiconductor substrate. The strained-silicon layer may be formed by a silicon epitaxial growth on the ion-implanted layer or by causing the ions to recoil into the semiconductor substrate with such energy that a region of the semiconductor substrate in the vicinity of the surface thereof is left substantially free of the ions, thereby forming a strained-silicon layer in the substantially ion-free region.
摘要翻译： 集成电路（IC）包括在其上具有离子的半导体衬底之上形成的CMOS器件，其通过离子反冲程序注入到半导体衬底中。 IC优选但不一定在CMOS器件中并入次0.1微米技术。 注入的离子可以优选为锗离子。 应变硅层优选但不一定形成在半导体衬底的离子注入层的上方。 应变硅层可以通过在离子注入层上的硅外延生长或通过使离子以这样的能量回到半导体衬底中形成，使得其表面附近的半导体衬底的区域基本上保持 没有离子，从而在基本上无离子的区域中形成应变硅层。
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