Invention Grant
- Patent Title: Wafer level chip scale packaging structure and method of fabricating the same
- Patent Title (中): 晶圆级芯片级封装结构及其制造方法
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Application No.: US11652088Application Date: 2007-01-11
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Publication No.: US08039935B2Publication Date: 2011-10-18
- Inventor: Shu-Ming Chang , Lee-Cheng Shen , Wei-Chung Lo
- Applicant: Shu-Ming Chang , Lee-Cheng Shen , Wei-Chung Lo
- Applicant Address: TW Hsinchu
- Assignee: Industrial Technology Research Institute
- Current Assignee: Industrial Technology Research Institute
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch and Birch, LLP
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
A wafer level chip scale packaging structure and the method of fabricating the same are provided to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the adjacent layers is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the adjacent layers will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.
Public/Granted literature
- US20070108629A1 Wafer level chip scale packaging structure and method of fabricating the same Public/Granted day:2007-05-17
Information query
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