Invention Grant
US08049114B2 Package substrate with a cavity, semiconductor package and fabrication method thereof
有权
具有空腔的封装衬底,半导体封装及其制造方法
- Patent Title: Package substrate with a cavity, semiconductor package and fabrication method thereof
- Patent Title (中): 具有空腔的封装衬底,半导体封装及其制造方法
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Application No.: US12408719Application Date: 2009-03-22
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Publication No.: US08049114B2Publication Date: 2011-11-01
- Inventor: Kuo-Ching Chen , Tsung-Yuan Chen , Cheng-Pin Chien
- Applicant: Kuo-Ching Chen , Tsung-Yuan Chen , Cheng-Pin Chien
- Applicant Address: TW Kwei-San Industrial Zone, Taoyuan
- Assignee: Unimicron Technology Corp.
- Current Assignee: Unimicron Technology Corp.
- Current Assignee Address: TW Kwei-San Industrial Zone, Taoyuan
- Agent Winston Hsu; Scott Margo
- Main IPC: H05K1/03
- IPC: H05K1/03

Abstract:
A method of making a package substrate includes providing a cladding sheet comprising a first metal layer, a second metal layer and an intermediate layer between the first and second metal layers; etching away a portion of the first metal layer to expose a portion of the intermediate layer thereby forming a metal island body; laminating a first copper clad on the cladding sheet comprising a first copper foil and a first insulating layer; patterning the first copper foil to form a first circuit trace; patterning the second metal layer to form a second circuit trace; removing the metal island body to form a cavity in the first insulating layer; and removing the intermediate layer from bottom of the cavity.
Public/Granted literature
- US20100236817A1 PACKAGE SUBSTRATE WITH A CAVITY, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF Public/Granted day:2010-09-23
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