发明授权
US08050042B2 Clock routing in multiple channel modules and bus systems and method for routing the same
失效
多通道模块和总线系统中的时钟路由及其路由方法
- 专利标题: Clock routing in multiple channel modules and bus systems and method for routing the same
- 专利标题(中): 多通道模块和总线系统中的时钟路由及其路由方法
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申请号: US11190561申请日: 2005-07-26
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公开(公告)号: US08050042B2公开(公告)日: 2011-11-01
- 发明人: Ravindranath T. Kollipara , David Nguyen , Belgacem Haba
- 申请人: Ravindranath T. Kollipara , David Nguyen , Belgacem Haba
- 申请人地址: US CA Sunnyvale
- 专利权人: Rambus Inc.
- 当前专利权人: Rambus Inc.
- 当前专利权人地址: US CA Sunnyvale
- 代理机构: Morgan, Lewis & Bockius LLP
- 主分类号: H05K7/02
- IPC分类号: H05K7/02 ; H05K7/06 ; H05K7/08 ; H05K7/10
摘要:
The terminating module and method include integrated circuits and a termination circuit which receive clock signals from the integrated circuit. The integrated circuit includes at least one memory integrated circuit mounted on a printed circuit board. An electrical connector is configured to couple the terminating module to a motherboard. Additionally, the termination circuit includes a resistor. In another embodiment, the terminating module provides a printed circuit board, a memory integrated circuit mounted on the circuit board, a terminator circuit which includes a resistor, and an electrical connector. The electrical connector couples the terminating module to a motherboard.
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