公开(公告)号：US20120001670A1

公开(公告)日：2012-01-05

申请号：US13235251

申请日：2011-09-16

申请人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

发明人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

IPC分类号： G06F1/04

CPC分类号： G11C5/04 ,  G06F13/409 ,  G11C5/00 ,  H05K1/023 ,  H05K1/117 ,  H05K1/141 ,  H05K1/147 ,  H05K1/148 ,  H05K7/1459 ,  H05K2201/10189

摘要： The terminating module includes integrated circuits and a termination circuit which receive clock signals from the integrated circuit. The integrated circuit includes at least one memory integrated circuit mounted on a printed circuit board. An electrical connector is configured to couple the terminating module to a motherboard. Additionally, the termination circuit includes a resistor. In another embodiment, the terminating module provides a printed circuit board, a memory integrated circuit mounted on the circuit board, a terminator circuit which includes a resistor, and an electrical connector. The electrical connector couples the terminating module to a motherboard.

摘要翻译： 终端模块包括集成电路和从集成电路接收时钟信号的终端电路。 集成电路包括安装在印刷电路板上的至少一个存储器集成电路。 电连接器被配置为将终端模块耦合到主板。 另外，终端电路包括电阻器。 在另一个实施例中，端接模块提供印刷电路板，安装在电路板上的存储器集成电路，包括电阻器和电连接器的终端电路。 电连接器将终端模块耦合到主板。

公开(公告)号：US08050042B2

公开(公告)日：2011-11-01

申请号：US11190561

申请日：2005-07-26

申请人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

发明人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

IPC分类号： H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC分类号： G11C5/04 ,  G06F13/409 ,  G11C5/00 ,  H05K1/023 ,  H05K1/117 ,  H05K1/141 ,  H05K1/147 ,  H05K1/148 ,  H05K7/1459 ,  H05K2201/10189

摘要： The terminating module and method include integrated circuits and a termination circuit which receive clock signals from the integrated circuit. The integrated circuit includes at least one memory integrated circuit mounted on a printed circuit board. An electrical connector is configured to couple the terminating module to a motherboard. Additionally, the termination circuit includes a resistor. In another embodiment, the terminating module provides a printed circuit board, a memory integrated circuit mounted on the circuit board, a terminator circuit which includes a resistor, and an electrical connector. The electrical connector couples the terminating module to a motherboard.

摘要翻译： 终端模块和方法包括集成电路和从集成电路接收时钟信号的终端电路。 集成电路包括安装在印刷电路板上的至少一个存储器集成电路。 电连接器被配置为将终端模块耦合到主板。 另外，终端电路包括电阻器。 在另一个实施例中，端接模块提供印刷电路板，安装在电路板上的存储器集成电路，包括电阻器和电连接器的终端电路。 电连接器将终端模块耦合到主板。

公开(公告)号：US07027307B2

公开(公告)日：2006-04-11

申请号：US10420308

申请日：2003-04-22

申请人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

发明人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

IPC分类号： H05K7/02 ,  H05K7/06 ,  H05K7/08

CPC分类号： G11C5/04 ,  G06F13/409 ,  G11C5/00 ,  H05K1/023 ,  H05K1/117 ,  H05K1/141 ,  H05K1/147 ,  H05K1/148 ,  H05K7/1459 ,  H05K2201/10189

摘要： An apparatus is provided, which includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit. The memory module that is positioned at the end of the order is unique in that it includes a clock signal terminating circuit connected to the last memory integrated circuit. With this configuration, a clock loop is formed by directly routing the clock signal from the output of the clock signal generating circuit through each of the memory modules in the order (without connecting to any of the intervening memory integrated circuits) to the memory integrated circuit positioned at the end of the order. Then, the clock signal is asserted on the previous memory modules by routing it back through the memory integrated circuits thereon, in reverse order to the memory integrated circuit positioned at the beginning of the order and from there to the memory interface circuit. To complete the clock loop, the clock signal is again asserted by routing it from the memory interface circuit back through the memory integrated circuits in order to the memory integrated circuit positioned at the end of the order. Finally, the clock signal is terminated at the clock signal terminating circuit on the memory module positioned at the end of the order.

公开(公告)号：US06590781B2

公开(公告)日：2003-07-08

申请号：US09817828

申请日：2001-03-26

申请人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

发明人： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

IPC分类号： H05K702

CPC分类号： G11C5/04 ,  G06F13/409 ,  G11C5/00 ,  H05K1/023 ,  H05K1/117 ,  H05K1/141 ,  H05K1/147 ,  H05K1/148 ,  H05K7/1459 ,  H05K2201/10189

摘要： An apparatus is provided, which includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit. The memory module that is positioned at the end of the order is unique in that it includes a clock signal terminating circuit connected to the last memory integrated circuit. With this configuration, a clock loop is formed by directly routing the clock signal from the output of the clock signal generating circuit through each of the memory modules in the order (without connecting to any of the intervening memory integrated circuits) to the memory integrated circuit positioned at the end of the order. Then, the clock signal is asserted on the previous memory modules by routing it back through the memory integrated circuits thereon, in reverse order to the memory integrated circuit positioned at the beginning of the order and from there to the memory interface circuit. To complete the clock loop, the clock signal is again asserted by routing it from the memory interface circuit back through the memory integrated circuits in order to the memory integrated circuit positioned at the end of the order. Finally, the clock signal is terminated at the clock signal terminating circuit on the memory module positioned at the end of the order.

摘要翻译： 提供了一种装置，其包括存储器接口电路，时钟信号发生电路和多个存储器电路。 存储器电路被可操作地耦合并按照多个存储器模块的顺序排列，使得位于该命令开始处的存储器模块被耦合到时钟信号发生电路和存储器接口电路的输出端。 定位在订单结尾的存储器模块是唯一的，因为它包括连接到最后存储器集成电路的时钟信号终端电路。 利用这种配置，通过将时钟信号发生电路的输出的时钟信号通过每个存储器模块以顺序（不连接到任何中间存储器集成电路）直​​接路由到存储器集成电路而形成时钟环路 定位在订单结束。 然后，时钟信号在先前的存储器模块上通过其上的存储器集成电路将其重新布置，以与定位在订单开始处的存储器集成电路相反，并且从那里到存储器接口电路。 为了完成时钟环路，时钟信号通过将存储器接口电路从存储器集成电路重新路由到存储器集成电路定位在订单结束处而被再次断言。 最后，时钟信号终止在位于订单结束的存储器模块上的时钟信号终端电路。

公开(公告)号：US06681338B1

公开(公告)日：2004-01-20

申请号：US09599091

申请日：2000-06-21

申请人： Ravindranath T. Kollipara

发明人： Ravindranath T. Kollipara

IPC分类号： G06F104

CPC分类号： H05K1/0248 ,  G06F1/10 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/097

摘要： Methods and systems for reducing signal skew caused by dielectric material variations within one or more module substrates are described. In one embodiment, an elongate module substrate having a long axis includes multiple signal routing layers supported by the module substrate. Multiple devices, such as memory devices (e.g. DRAMs) are supported by the module substrate and are operably connected with the signal routing layers. Multiple skew-reducing locations (e.g. vias) within the module permit signals that are routed in two or more of the multiple signal routing layers to be switched to a different signal routing layer. The skew-reducing locations can be arranged in at least one line that is generally transverse the long axis of the module substrate. The lines of skew-reducing locations can be disposed at various locations on the module. For example, a line of skew-reducing locations can be disposed proximate the middle of the module to effectively offset skew. Multiple skew-reducing locations can be provided at other locations within the module as well so that the signals are switched multiple different times as they propagate through the module.

摘要翻译： 描述了用于减少由一个或多个模块基板内的电介质材料变化引起的信号偏斜的方法和系统。 在一个实施例中，具有长轴的细长模块衬底包括由模块衬底支撑的多个信号路由层。 诸如存储器件（例如DRAM）的多个器件由模块衬底支持并且与信号布线层可操作地连接。 模块内的多个偏斜减少位置（例如，过孔）允许在多个信号路由层中的两个或多个路由层中路由的信号被切换到不同的信号路由层。 偏斜减少位置可以布置在通常横向模块基板的长轴的至少一条线中。 偏斜减少位置的线可以设置在模块上的各个位置。 例如，一排偏斜减少位置可以靠近模块的中间设置，以有效地抵消偏移。 也可以在模块内的其他位置提供多个偏斜减少位置，以便信号在传播通过模块时被多次切换。