发明授权
US08093070B2 Method for leakage reduction in fabrication of high-density FRAM arrays
有权
高密度FRAM阵列制造中泄漏减少的方法
- 专利标题: Method for leakage reduction in fabrication of high-density FRAM arrays
- 专利标题(中): 高密度FRAM阵列制造中泄漏减少的方法
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申请号: US11706722申请日: 2007-02-15
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公开(公告)号: US08093070B2公开(公告)日: 2012-01-10
- 发明人: Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
- 申请人: Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
- 申请人地址: US TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: US TX Dallas
- 代理商 John J. Patti; Wade J. Brady, III; Frederick J. Telecky, Jr.
- 主分类号: H01L21/00
- IPC分类号: H01L21/00
摘要:
A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.
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