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1.发明授权公开(公告)号：US08093070B2
公开(公告)日：2012-01-10
申请号：US11706722
申请日：2007-02-15
申请人： Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
发明人： Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
IPC分类号： H01L21/00
CPC分类号： H01L28/75 , H01L27/11507 , H01L28/55
摘要： A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.
摘要翻译： 提供一种用于制造铁电电容器结构的方法，其包括在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法。 该方法包括蚀刻上电极的部分，蚀刻铁电材料，并蚀刻下电极以限定图案化的铁电电容器结构，以及蚀刻下电极扩散阻挡结构的一部分。 所述方法还包括使用第一灰化过程灰化所述图案化的铁电电容器结构，其中所述灰分包括含氧/氮/水的灰分，在所述第一灰化处理之后执行湿式清洁处理，以及使用 第二次灰化过程。
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2.发明申请公开(公告)号：US20080081380A1
公开(公告)日：2008-04-03
申请号：US11706722
申请日：2007-02-15
申请人： Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
发明人： Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
IPC分类号： H01L21/00
CPC分类号： H01L28/75 , H01L27/11507 , H01L28/55
摘要： A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.
摘要翻译： 提供一种用于制造铁电电容器结构的方法，其包括在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法。 该方法包括蚀刻上电极的部分，蚀刻铁电材料，并蚀刻下电极以限定图案化的铁电电容器结构，以及蚀刻下电极扩散阻挡结构的一部分。 所述方法还包括使用第一灰化过程灰化所述图案化的铁电电容器结构，其中所述灰分包括含氧/氮/水的灰分，在所述第一灰化处理之后执行湿式清洁处理，以及使用 第二次灰化过程。
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公开(公告)号：US20090194801A1
公开(公告)日：2009-08-06
申请号：US12025207
申请日：2008-02-04
申请人： Francis Gabriel Celii , Robert Kraft , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Theodore S. Moise
发明人： Francis Gabriel Celii , Robert Kraft , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Theodore S. Moise
CPC分类号： H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.
摘要翻译： 一种制造半导体器件的方法。 该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的铁电层，其中作为图案化的副产品，在铁电电容器的侧壁上产生导电残留物。 该方法还包括使用包括保持大于约60℃的衬底温度的物理等离子体蚀刻清理工艺去除导电残留物。
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公开(公告)号：US20070298521A1
公开(公告)日：2007-12-27
申请号：US11669759
申请日：2007-01-31
申请人： Yaw S. Obeng , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Sanjeev Aggarwal , Francis Gabriel Celii , Lindsey H. Hall , Robert Kraft , Theodore S. Moise
发明人： Yaw S. Obeng , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Sanjeev Aggarwal , Francis Gabriel Celii , Lindsey H. Hall , Robert Kraft , Theodore S. Moise
IPC分类号： H01L21/00
CPC分类号： H01L21/02071 , H01L21/02129 , H01L21/02164 , H01L21/0217 , H01L21/02175 , H01L21/022 , H01L21/02263 , H01L21/31683 , H01L28/55 , H01L28/65
摘要： A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.
摘要翻译： 提出了制造半导体器件的方法。 一方面，该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的电极和铁电层，其中在铁电电容器的侧壁上产生导电的含贵金属的聚合物。 该方法还包括将含导电贵金属的聚合物转化为非导电金属氧化物。 转化包括从含导电贵金属的聚合物形成水溶性金属盐，并使水溶性金属盐与酸性水溶液反应，形成金属氢氧化物。 转化还包括氧化金属氢氧化物以形成非导电金属氧化物。
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公开(公告)号：US07723199B2
公开(公告)日：2010-05-25
申请号：US11669759
申请日：2007-01-31
申请人： Yaw S. Obeng , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Sanjeev Aggarwal , Francis Gabriel Celii , Lindsey H. Hall , Robert Kraft , Theodore S. Moise
发明人： Yaw S. Obeng , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Sanjeev Aggarwal , Francis Gabriel Celii , Lindsey H. Hall , Robert Kraft , Theodore S. Moise
IPC分类号： H01L21/02
CPC分类号： H01L21/02071 , H01L21/02129 , H01L21/02164 , H01L21/0217 , H01L21/02175 , H01L21/022 , H01L21/02263 , H01L21/31683 , H01L28/55 , H01L28/65
摘要： A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.
摘要翻译： 提出了制造半导体器件的方法。 一方面，该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的电极和铁电层，其中在铁电电容器的侧壁上产生导电的含贵金属的聚合物。 该方法还包括将含导电贵金属的聚合物转化为非导电金属氧化物。 转化包括从含导电贵金属的聚合物形成水溶性金属盐，并使水溶性金属盐与酸性水溶液反应，形成金属氢氧化物。 转化还包括氧化金属氢氧化物以形成非导电金属氧化物。
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公开(公告)号：US07985603B2
公开(公告)日：2011-07-26
申请号：US12025207
申请日：2008-02-04
申请人： Francis Gabriel Celii , Robert Kraft , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Theodore S. Moise
发明人： Francis Gabriel Celii , Robert Kraft , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Theodore S. Moise
CPC分类号： H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.
摘要翻译： 一种制造半导体器件的方法。 该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的铁电层，其中作为图案化的副产品，在铁电电容器的侧壁上产生导电残留物。 该方法还包括使用包括保持大于约60℃的衬底温度的物理等离子体蚀刻清理工艺去除导电残留物。
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公开(公告)号：US06841396B2
公开(公告)日：2005-01-11
申请号：US10440697
申请日：2003-05-19
IPC分类号： H01L21/00 , H01L21/20 , H01L21/8242 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A ferroelectric memory device comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereof for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and reference voltage on the second bit line.
摘要翻译： 铁电存储器件包括逻辑可编程电容参考电路。 电路适于在感测操作模式期间产生参考电压，其中参考电压包括作为一个以上存储器条件的函数的值。 存储器件还包括位线对，其中位线对的第一位线具有耦合的铁电电容器用于感测位线对，并且位线对的第二位线耦合到参考电压。 感测电路耦合到位线对，并且被配置为使用与第一位线相关联的电压和第二位线上的参考电压来检测与铁电电容器相关联的数据状态。
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公开(公告)号：US07811882B2
公开(公告)日：2010-10-12
申请号：US12353172
申请日：2009-01-13
IPC分类号： H01L21/8242
CPC分类号： H01L27/11507 , H01G4/33 , H01L28/55
摘要： A method of manufacturing a semiconductor device. The method comprises fabricating a ferroelectric capacitor. The capacitor's fabrication includes forming conductive and ferroelectric material layers on a semiconductor substrate, forming a hardmask layer on the conductive and ferroelectric material layers, forming an organic bottom antireflective coating layer on the hardmask layer, and, patterning the organic bottom antireflective coating layer. Seasoning in a hardmask etching chamber is substantially unaffected by the patterning.
摘要翻译： 一种制造半导体器件的方法。 该方法包括制造铁电电容器。 电容器的制造包括在半导体衬底上形成导电和铁电材料层，在导电和铁电材料层上形成硬掩模层，在硬掩模层上形成有机底部抗反射涂层，以及图案化有机底部抗反射涂层。 硬掩模蚀刻室中的调味基本上不受图案化的影响。
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公开(公告)号：US20100176427A1
公开(公告)日：2010-07-15
申请号：US12353172
申请日：2009-01-13
IPC分类号： H01L29/86 , H01L21/00 , H01L21/28 , H01L21/336 , H01L21/8246
CPC分类号： H01L27/11507 , H01G4/33 , H01L28/55
摘要： A method of manufacturing a semiconductor device. The method comprises fabricating a ferroelectric capacitor. The capacitor's fabrication includes forming conductive and ferroelectric material layers on a semiconductor substrate, forming a hardmask layer on the conductive and ferroelectric material layers, forming an organic bottom antireflective coating layer on the hardmask layer, and, patterning the organic bottom antireflective coating layer. Seasoning in a hardmask etching chamber is substantially unaffected by the patterning.
摘要翻译： 一种制造半导体器件的方法。 该方法包括制造铁电电容器。 电容器的制造包括在半导体衬底上形成导电和铁电材料层，在导电和铁电材料层上形成硬掩模层，在硬掩模层上形成有机底部抗反射涂层，以及图案化有机底部抗反射涂层。 硬掩模蚀刻室中的调味基本上不受图案化的影响。
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