公开(公告)号：US08496842B2

公开(公告)日：2013-07-30

申请号：US13230350

申请日：2011-09-12

Applicant: Kezhakkedath R. Udayakumar ,  Marie Denison ,  Ted S. Moise

Inventor： Kezhakkedath R. Udayakumar ,  Marie Denison ,  Ted S. Moise

IPC: B44C1/22

CPC classification number: H01L41/08 ,  H01L27/20 ,  H01L41/0533 ,  H01L41/1134 ,  H01L41/1136 ,  H01L41/1138 ,  H01L41/22 ,  H01L41/318 ,  H01L2224/18

Abstract: A planar integrated MEMS device has a piezoelectric element on a dielectric isolation layer over a flexible element attached to a proof mass. The piezoelectric element contains a ferroelectric element with a perovskite structure formed over an isolation dielectric. At least two electrodes are formed on the ferroelectric element. An upper hydrogen barrier is formed over the piezoelectric element. Front side singulation trenches are formed at a periphery of the MEMS device extending into the semiconductor substrate. A DRIE process removes material from the bottom side of the substrate to form the flexible element, removes material from the substrate under the front side singulation trenches, and forms the proof mass from substrate material. The piezoelectric element overlaps the flexible element.

Abstract translation: 平面集成MEMS器件在连接到校准块的柔性元件上的介电隔离层上具有压电元件。 压电元件包含在隔离电介质上形成的具有钙钛矿结构的铁电元件。 在铁电元件上形成至少两个电极。 在压电元件上形成上部氢屏障。 在延伸到半导体衬底中的MEMS器件的周边形成有正面侧划分沟槽。 DRIE工艺从衬底的底侧去除材料以形成柔性元件，在正面单面沟槽之下从衬底去除材料，并从衬底材料形成校验物质。 压电元件与柔性元件重叠。

公开(公告)号：US20120228739A1

公开(公告)日：2012-09-13

申请号：US13480044

申请日：2012-05-24

Applicant: Kezhakkedath R. Udayakumar ,  Scott R. Summerfelt ,  Ted S. Moise ,  Manoj K. Jain

Inventor： Kezhakkedath R. Udayakumar ,  Scott R. Summerfelt ,  Ted S. Moise ,  Manoj K. Jain

IPC: H01L29/92

CPC classification number: H01L21/76843 ,  H01L27/11509 ,  H01L28/57

Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.

Abstract translation: 包含FeCap阵列的集成电路。 FeCap阵列在侧面至少部分地被氢阻挡壁包围，并且在顶部被氢阻挡顶板包围。 一种用于至少部分地封闭具有氢阻挡壁和氢阻挡顶板的FeCap阵列的方法。

公开(公告)号：US20090275147A1

公开(公告)日：2009-11-05

申请号：US12502523

申请日：2009-07-14

Applicant: Kezhakkedath R. UDAYAKUMAR ,  Lindsey H. HALL ,  Francis G. CELII ,  Scott R. SUMMERFELT

Inventor： Kezhakkedath R. UDAYAKUMAR ,  Lindsey H. HALL ,  Francis G. CELII ,  Scott R. SUMMERFELT

IPC: H01L21/00

CPC classification number: H01L21/31122 ,  H01L21/0206 ,  H01L21/02071 ,  H01L21/32136 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/65

Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.

Abstract translation: 制造铁电存储器件，同时减轻边缘退化。 在一个或多个半导体层上形成底部电极。 在底部电极上形成铁电层。 顶部电极形成在铁电层上。 上电极，铁电层和底电极被图案化或蚀刻。 进行干洗以减轻边缘退化。 然后进行湿蚀刻/清洁。

公开(公告)号：US07304881B2

公开(公告)日：2007-12-04

申请号：US10880406

申请日：2004-06-28

Applicant: John Anthony Rodriguez ,  Kezhakkedath R. Udayakumar

Inventor： John Anthony Rodriguez ,  Kezhakkedath R. Udayakumar

IPC: G11C11/22

CPC classification number: G11C11/5657 ,  G11C11/22 ,  G11C2211/5641

Abstract: Apparatus and methods are described for a multi-level FeRAM memory device. Using write and read circuits associated with the memory device, multiple data states may be written to and read from the ferroelectric memory device which are associated with a single polarization direction, thereby allowing for a single cell to contain more than one bit of data.

Abstract translation: 描述了用于多级FeRAM存储器件的装置和方法。 使用与存储器件相关联的写入和读取电路，可以将多个数据状态写入到与单个极化方向相关联的铁电存储器件并从其读取，从而允许单个单元包含多于一个位的数据。

公开(公告)号：US08058677B2

公开(公告)日：2011-11-15

申请号：US12396976

申请日：2009-03-03

Applicant: Scott R. Summerfelt ,  Kezhakkedath R. Udayakumar ,  John P. Campbell ,  Hugh P. McAdams

Inventor： Scott R. Summerfelt ,  Kezhakkedath R. Udayakumar ,  John P. Campbell ,  Hugh P. McAdams

IPC: H01L23/28

CPC classification number: H01L23/3135 ,  H01L23/562 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.

公开(公告)号：US20110062550A1

公开(公告)日：2011-03-17

申请号：US12718691

申请日：2010-03-05

Applicant: Kezhakkedath R. Udayakumar ,  Scott R. Summerfelt ,  Ted S. Moise ,  Manoj K. Jain

Inventor： Kezhakkedath R. Udayakumar ,  Scott R. Summerfelt ,  Ted S. Moise ,  Manoj K. Jain

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L21/76843 ,  H01L27/11509 ,  H01L28/57

Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.

Abstract translation: 包含FeCap阵列的集成电路。 FeCap阵列在侧面至少部分地被氢阻挡壁包围，并且在顶部被氢阻挡顶板包围。 一种用于至少部分地封闭具有氢阻挡壁和氢阻挡顶板的FeCap阵列的方法。

公开(公告)号：US07772014B2

公开(公告)日：2010-08-10

申请号：US11845834

申请日：2007-08-28

Applicant: Kezhakkedath R. Udayakumar ,  Ted S. Moise ,  Qi-Du Jiang

Inventor： Kezhakkedath R. Udayakumar ,  Ted S. Moise ,  Qi-Du Jiang

IPC: H01L29/92

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/57

Abstract: One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The first barrier layer is formed by depositing multiple barrier layers and densifying each of the barrier layers after its deposition. This forms a stack of multiple barrier layers of a same elemental composition. The method further includes forming a second barrier layer over the first barrier layer and forming a lower capacitor electrode, a ferroelectric dielectric layer over the lower capacitor, and forming an upper capacitor electrode over the ferroelectric dielectric layer. A device made by this method is also provided herein.

Abstract translation: 本发明的一个方面提供一种制造具有减少单位故障的FeRAM半导体器件的方法。 该方面包括在位于半导体衬底之上的电介质层内形成电接触，并在电介质层和电接触之上形成第一阻挡层。 第一阻挡层通过沉积多个阻挡层并在其沉积之后致密化每个阻挡层而形成。 这形成了具有相同元素组成的多个阻挡层的堆叠。 该方法还包括在第一阻挡层上形成第二阻挡层，并形成下电容器电极，在下电容器上形成铁电电介质层，以及在铁电介质层上形成上电容器电极。 本文还提供了通过该方法制造的装置。

公开(公告)号：US07572698B2

公开(公告)日：2009-08-11

申请号：US11442810

申请日：2006-05-30

Applicant: Kezhakkedath R. Udayakumar ,  Lindsey H. Hall ,  Francis G. Celii ,  Scott R. Summerfelt

Inventor： Kezhakkedath R. Udayakumar ,  Lindsey H. Hall ,  Francis G. Celii ,  Scott R. Summerfelt

IPC: H01L21/336

CPC classification number: H01L21/31122 ,  H01L21/0206 ,  H01L21/02071 ,  H01L21/32136 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/65

Abstract: A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.

Abstract translation: 制造铁电存储器件，同时减轻边缘退化。 在一个或多个半导体层上形成底部电极。 在底部电极上形成铁电层。 顶部电极形成在铁电层上。 上电极，铁电层和底电极被图案化或蚀刻。 进行干洗以减轻边缘退化。 然后进行湿蚀刻/清洁。

公开(公告)号：US20090194801A1

公开(公告)日：2009-08-06

申请号：US12025207

申请日：2008-02-04

Applicant: Francis Gabriel Celii ,  Robert Kraft ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Theodore S. Moise

Inventor： Francis Gabriel Celii ,  Robert Kraft ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Theodore S. Moise

IPC: H01L27/00 ,  H01L21/00

CPC classification number: H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

Abstract: A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.

Abstract translation: 一种制造半导体器件的方法。 该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的铁电层，其中作为图案化的副产品，在铁电电容器的侧壁上产生导电残留物。 该方法还包括使用包括保持大于约60℃的衬底温度的物理等离子体蚀刻清理工艺去除导电残留物。

公开(公告)号：US08779485B2

公开(公告)日：2014-07-15

申请号：US13480044

申请日：2012-05-24

Applicant: Kezhakkedath R. Udayakumar ,  Scott R. Summerfelt ,  Ted S. Moise ,  Manoj K. Jain

Inventor： Kezhakkedath R. Udayakumar ,  Scott R. Summerfelt ,  Ted S. Moise ,  Manoj K. Jain

IPC: H01L21/02 ,  H01L23/48 ,  H01L21/768 ,  H01L49/02 ,  H01L27/115

CPC classification number: H01L21/76843 ,  H01L27/11509 ,  H01L28/57

Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.