发明授权
US08098533B2 Semiconductor memory device with adjustable selected word line potential under low voltage condition
有权
半导体存储器件,在低电压条件下具有可选择的字线电位
- 专利标题: Semiconductor memory device with adjustable selected word line potential under low voltage condition
- 专利标题(中): 半导体存储器件,在低电压条件下具有可选择的字线电位
-
申请号: US12457936申请日: 2009-06-25
-
公开(公告)号: US08098533B2公开(公告)日: 2012-01-17
- 发明人: Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
- 申请人: Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
- 申请人地址: JP Kawasaki-shi, Kanagawa
- 专利权人: Renesas Electronics Corporation
- 当前专利权人: Renesas Electronics Corporation
- 当前专利权人地址: JP Kawasaki-shi, Kanagawa
- 代理机构: Buchanan Ingersoll & Rooney PC
- 优先权: JP2005-224258 20050802; JP2006-143014 20060523
- 主分类号: G11C7/00
- IPC分类号: G11C7/00
摘要:
A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.
公开/授权文献
信息查询