发明授权
US08101516B2 Method of forming contact hole pattern in semiconductor integrated circuit device
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在半导体集成电路器件中形成接触孔图案的方法
- 专利标题： Method of forming contact hole pattern in semiconductor integrated circuit device
- 专利标题（中）： 在半导体集成电路器件中形成接触孔图案的方法
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申请号： US11857275申请日： 2007-09-18
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公开(公告)号： US08101516B2公开(公告)日： 2012-01-24
- 发明人: Toshiya Kotani , Hiroko Nakamura , Koji Hashimoto
- 申请人： Toshiya Kotani , Hiroko Nakamura , Koji Hashimoto
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- 优先权： JP2006-254709 20060920
- 主分类号： H01L21/4763
- IPC分类号： H01L21/4763
摘要：
A block film is formed on a region which includes a region of an insulating layer where a first hole is to be formed, and in which no second hole is to be formed, and a resist film having openings for forming the first and second holes is formed on the block film and insulating layer. Etching is performed by using the resist film as a mask, thereby forming the first hole in the block film and insulating layer, and the second hole in the insulating layer. The depth of the first hole from the upper surface of the insulating layer is smaller than that of the second hole, so the first hole does not reach the semiconductor substrate.
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