公开(公告)号：US08101516B2

公开(公告)日：2012-01-24

申请号：US11857275

申请日：2007-09-18

申请人： Toshiya Kotani ,  Hiroko Nakamura ,  Koji Hashimoto

发明人： Toshiya Kotani ,  Hiroko Nakamura ,  Koji Hashimoto

IPC分类号： H01L21/4763

CPC分类号： H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

摘要： A block film is formed on a region which includes a region of an insulating layer where a first hole is to be formed, and in which no second hole is to be formed, and a resist film having openings for forming the first and second holes is formed on the block film and insulating layer. Etching is performed by using the resist film as a mask, thereby forming the first hole in the block film and insulating layer, and the second hole in the insulating layer. The depth of the first hole from the upper surface of the insulating layer is smaller than that of the second hole, so the first hole does not reach the semiconductor substrate.

摘要翻译： 在包括要形成第一孔的绝缘层的区域，并且不形成第二孔的区域上形成阻挡膜，并且具有用于形成第一孔和第二孔的开口的抗蚀剂膜是 形成在阻挡膜和绝缘层上。 通过使用抗蚀剂膜作为掩模进行蚀刻，从而在阻挡膜和绝缘层中形成第一孔，并在绝缘层中形成第二孔。 绝缘层的上表面的第一孔的深度小于第二孔的深度，所以第一孔不到达半导体衬底。

公开(公告)号：US20080070402A1

公开(公告)日：2008-03-20

申请号：US11857275

申请日：2007-09-18

申请人： Toshiya Kotani ,  Hiroko Nakamura ,  Koji Hashimoto

发明人： Toshiya Kotani ,  Hiroko Nakamura ,  Koji Hashimoto

IPC分类号： H01L21/4763 ,  H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

摘要： A block film is formed on a region which includes a region of an insulating layer where a first hole is to be formed, and in which no second hole is to be formed, and a resist film having openings for forming the first and second holes is formed on the block film and insulating layer. Etching is performed by using the resist film as a mask, thereby forming the first hole in the block film and insulating layer, and the second hole in the insulating layer. The depth of the first hole from the upper surface of the insulating layer is smaller than that of the second hole, so the first hole does not reach the semiconductor substrate.

摘要翻译： 在包括要形成第一孔的绝缘层的区域，并且不形成第二孔的区域上形成阻挡膜，并且具有用于形成第一孔和第二孔的开口的抗蚀剂膜是 形成在阻挡膜和绝缘层上。 通过使用抗蚀剂膜作为掩模进行蚀刻，从而在阻挡膜和绝缘层中形成第一孔，并在绝缘层中形成第二孔。 绝缘层的上表面的第一孔的深度小于第二孔的深度，所以第一孔不到达半导体衬底。

公开(公告)号：US20090011370A1

公开(公告)日：2009-01-08

申请号：US12136368

申请日：2008-06-10

申请人： Hiroko Nakamura ,  Koji Hashimoto ,  Soichi Inoue ,  Toshiya Kotani

发明人： Hiroko Nakamura ,  Koji Hashimoto ,  Soichi Inoue ,  Toshiya Kotani

IPC分类号： G03F7/22

CPC分类号： G03F7/0035 ,  G03F7/091

摘要： A pattern forming method using two layers of resist pattern stacked one on the other has been disclosed. First, a first resist pattern is formed on a to-be-processed film. The first resist pattern is slimmed. On the slimmed first resist pattern and to-be-processed film, a second resist pattern is formed. With the first and second resist patterns as a mask, the film is processed.

摘要翻译： 已经公开了使用彼此堆叠的两层抗蚀剂图案的图案形成方法。 首先，在被处理膜上形成第一抗蚀剂图案。 第一种抗蚀剂图案纤薄。 在细长的第一抗蚀剂图案和被处理膜上，形成第二抗蚀剂图案。 利用第一和第二抗蚀剂图案作为掩模，处理该膜。

公开(公告)号：US09207531B2

公开(公告)日：2015-12-08

申请号：US13239449

申请日：2011-09-22

申请人： Hiroko Nakamura ,  Koji Asakawa ,  Shigeki Hattori ,  Satoshi Tanaka ,  Toshiya Kotani

发明人： Hiroko Nakamura ,  Koji Asakawa ,  Shigeki Hattori ,  Satoshi Tanaka ,  Toshiya Kotani

IPC分类号： H01L21/31 ,  H01L21/469 ,  G03F7/00 ,  B81C1/00 ,  B82Y10/00 ,  B82Y40/00

CPC分类号： G03F7/0002 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y40/00

摘要： According to one embodiment, a pattern including first and second block phases is formed by self-assembling a block copolymer onto a film to be processed. The entire block copolymer present in a first region is removed under a first condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in a region other than the first region. The first block phase present in a second region is selectively removed under a second condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in an overlap region between a region other than the first region and a region other than the second region, and leaving a pattern of second block phase in the second region excluding the overlap region. The film is etched with the left patterns as masks.

摘要翻译： 根据一个实施方案，通过将嵌段共聚物自组装成待加工的膜来形成包括第一和第二嵌段相的图案。 存在于第一区域中的整个嵌段共聚物在第一条件下通过进行能量束照射和显影而除去，从而在第一区域以外的区域留下包括第一和第二嵌段相的图案。 存在于第二区域中的第一块相位通过进行能量束照射和显影而在第二条件下被选择性地去除，从而在包括第一区域和第一区域之间的重叠区域中留下包括第一和第二块相的图案， 区域，并且在除了重叠区域之外的第二区域中留下第二块相位的图案。 用左图案蚀刻该胶片作为掩模。

公开(公告)号：US20120127454A1

公开(公告)日：2012-05-24

申请号：US13239449

申请日：2011-09-22

申请人： Hiroko NAKAMURA ,  Koji Asakawa ,  Shigeki Hattori ,  Satoshi Tanaka ,  Toshiya Kotani

发明人： Hiroko NAKAMURA ,  Koji Asakawa ,  Shigeki Hattori ,  Satoshi Tanaka ,  Toshiya Kotani

IPC分类号： G03B27/32

CPC分类号： G03F7/0002 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y40/00

摘要： According to one embodiment, a pattern including first and second block phases is formed by self-assembling a block copolymer onto a film to be processed. The entire block copolymer present in a first region is removed under a first condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in a region other than the first region. The first block phase present in a second region is selectively removed under a second condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in an overlap region between a region other than the first region and a region other than the second region, and leaving a pattern of second block phase in the second region excluding the overlap region. The film is etched with the left patterns as masks.

摘要翻译： 根据一个实施方案，通过将嵌段共聚物自组装成待加工的膜来形成包括第一和第二嵌段相的图案。 存在于第一区域中的整个嵌段共聚物在第一条件下通过进行能量束照射和显影而除去，从而在第一区域以外的区域留下包括第一和第二嵌段相的图案。 存在于第二区域中的第一块相位通过进行能量束照射和显影而在第二条件下被选择性地去除，从而在包括第一区域和第一区域之间的重叠区域中留下包括第一和第二块相的图案， 区域，并且在除了重叠区域之外的第二区域中留下第二块相位的图案。 用左图案蚀刻该胶片作为掩模。

公开(公告)号：US07560197B2

公开(公告)日：2009-07-14

申请号：US11061599

申请日：2005-02-22

申请人： Hiroko Nakamura ,  Toshiya Kotani ,  Satoshi Tanaka ,  Shoji Mimotogi

发明人： Hiroko Nakamura ,  Toshiya Kotani ,  Satoshi Tanaka ,  Shoji Mimotogi

IPC分类号： G03F1/06

CPC分类号： G03F7/0035 ,  G03F1/92 ,  G03F7/40

摘要： A mask pattern data producing method is disclosed, which comprises preparing design pattern data in which contact holes are arranged on part of the grid points in matrix, preparing first mask pattern data in which first opening patterns are arranged on all of the grid points, and designing second mask pattern data in which second opening patterns and third opening patterns are arranged, the second opening patterns being arranged on the grid points at which the contact holes are arranged in the design pattern data to include the first opening patterns, the third opening patterns being arranged on a pair of grid points, which is a pair of diagonal grid points only on which the contact holes are arranged in a unit grid formed by four grid points, to include the first opening patterns arranged on the pair of grid points, in place of the second opening patterns.

摘要翻译： 公开了一种掩模图案数据制作方法，其特征在于，准备设置图形数据，其中接触孔被布置在矩阵中的网格点的一部分上，准备在所有网格点上布置第一开口图案的第一掩模图案数据，以及 设计其中布置有第二开口图案和第三开口图案的第二掩模图案数据，第二开口图案布置在布置在设计图案数据中的接触孔的网格点上以包括第一开口图案，第三开口图案 布置在一对栅格点上，该对栅格点仅在其上以4个格栅点形成的单位格栅布置在其上，以包括布置在该对网格点上的第一开口图案， 第二个打开模式的地方。

公开(公告)号：US20050196684A1

公开(公告)日：2005-09-08

申请号：US11061599

申请日：2005-02-22

申请人： Hiroko Nakamura ,  Toshiya Kotani ,  Satoshi Tanaka ,  Shoji Mimotogi

发明人： Hiroko Nakamura ,  Toshiya Kotani ,  Satoshi Tanaka ,  Shoji Mimotogi

IPC分类号： G03F1/92 ,  G03C5/00 ,  G03F9/00 ,  G06F17/50

CPC分类号： G03F7/0035 ,  G03F1/92 ,  G03F7/40

摘要： A mask pattern data producing method is disclosed, which comprises preparing design pattern data in which contact holes are arranged on part of the grid points in matrix, preparing first mask pattern data in which first opening patterns are arranged on all of the grid points, and designing second mask pattern data in which second opening patterns and third opening patterns are arranged, the second opening patterns being arranged on the grid points at which the contact holes are arranged in the design pattern data to include the first opening patterns, the third opening patterns being arranged on a pair of grid points, which is a pair of diagonal grid points only on which the contact holes are arranged in a unit grid formed by four grid points, to include the first opening patterns arranged on the pair of grid points, in place of the second opening patterns.

摘要翻译： 公开了一种掩模图案数据制作方法，其特征在于，准备设置图形数据，其中接触孔被布置在矩阵中的网格点的一部分上，准备在所有网格点上布置第一开口图案的第一掩模图案数据，以及 设计其中布置有第二开口图案和第三开口图案的第二掩模图案数据，第二开口图案布置在布置在设计图案数据中的接触孔的网格点上以包括第一开口图案，第三开口图案 布置在一对栅格点上，该对栅格点仅在其上以4个格栅点形成的单位格栅布置在其上，以包括布置在该对网格点上的第一开口图案， 第二个打开模式的地方。

公开(公告)号：US08142961B2

公开(公告)日：2012-03-27

申请号：US12717914

申请日：2010-03-04

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Koji Hashimoto ,  Soichi Inoue

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Koji Hashimoto ,  Soichi Inoue

IPC分类号： G03F1/00

CPC分类号： G06F17/5068 ,  G03F1/36

摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.

摘要翻译： 公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件 并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。

公开(公告)号：US07120882B2

公开(公告)日：2006-10-10

申请号：US11105431

申请日：2005-04-14

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Koji Hashimoto ,  Soichi Inoue ,  Ichiro Mori

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Koji Hashimoto ,  Soichi Inoue ,  Ichiro Mori

IPC分类号： G06F17/50

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.

摘要翻译： 公开了一种设置用于制造半导体集成电路的工艺参数的方法，包括通过使用工艺参数信息来校正第一图案以获得第二图案，第一图案是对应于半导体集成电路的设计布局的图案 ，通过使用处理参数信息来预测第三图案，在蚀刻工艺中，第三图案是对应于第二图案并且将形成在半导体晶片上的图案，通过将第三图案与第一图案进行比较来获得评估值 判定评估值是否满足预设条件，以及当评估值不满足预设条件时，改变处理参数信息。

公开(公告)号：US07090949B2

公开(公告)日：2006-08-15

申请号：US10724738

申请日：2003-12-02

申请人： Shigeki Nojima ,  Shoji Mimotogi ,  Satoshi Tanaka ,  Toshiya Kotani ,  Shigeru Hasebe ,  Koji Hashimoto ,  Soichi Inoue ,  Osamu Ikenaga

发明人： Shigeki Nojima ,  Shoji Mimotogi ,  Satoshi Tanaka ,  Toshiya Kotani ,  Shigeru Hasebe ,  Koji Hashimoto ,  Soichi Inoue ,  Osamu Ikenaga

IPC分类号： G01F9/00

CPC分类号： G03F1/36 ,  G03F1/68

摘要： Disclosed is a method of manufacturing a photo mask comprising preparing mask data for a mask pattern to be formed on a mask substrate, calculating edge moving sensitivity with respect to each of patterns included in the mask pattern using the mask data, the edge moving sensitivity corresponding to a difference between a proper exposure dose and an exposure dose to be set when a pattern edge varies, determining a monitor portion of the mask pattern, based on the calculated edge moving sensitivity, actually forming the mask pattern on the mask substrate, acquiring a dimension of a pattern included in that portion of the mask pattern formed on the mask substrate which corresponds to the monitor portion, determining evaluation value for the mask pattern formed on the mask substrate, based on the acquired dimension, and determining whether the evaluation value satisfies predetermined conditions.

摘要翻译： 公开了一种制造光掩模的方法，其包括：对掩模基板上形成的掩模图案准备掩模数据，使用掩模数据计算相对于包含在掩模图案中的每个图案的边缘移动灵敏度，边缘移动灵敏度对应 对于在图案边缘变化时要设置的适当曝光剂量和曝光剂量之间的差异，基于计算出的边缘移动灵敏度确定掩模图案的监视部分，实际在掩模基板上形成掩模图案，获取 基于所获取的尺寸，确定在掩模基板上形成的掩模图案的评估值，并且确定评估值是否满足的掩模图案的形成在掩模基板上的对应于监视部分的掩模图案的部分中的图案的尺寸 预定条件。