Invention Grant
- Patent Title: Method and system for representing manufacturing and lithography information for IC routing
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Application No.: US12276263Application Date: 2008-11-21
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Publication No.: US08103986B2Publication Date: 2012-01-24
- Inventor: Louis Scheffer
- Applicant: Louis Scheffer
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed.
Public/Granted literature
- US20090077520A1 Method and System for Representing Manufacturing and Lithography Information for IC Routing Public/Granted day:2009-03-19
Information query
