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    Method and System for Context-Specific Mask Inspection
    1.
    发明申请
    Method and System for Context-Specific Mask Inspection 有权
    上下文特定掩模检查的方法和系统

    公开(公告)号：US20070233419A1

    公开(公告)日：2007-10-04

    申请号：US11760715

    申请日：2007-06-08

    Applicant: Robert Pack ,  Louis Scheffer

    Inventor： Robert Pack ,  Louis Scheffer

    IPC: G06F19/00

    CPC classification number: G03F1/84

    Abstract: A method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to inspect a mask.

    Abstract translation: 用于检查光刻掩模的方法包括生成集成电路设计数据并使用来自集成电路设计数据的上下文信息来检查掩模。

    System and method for statistical design rule checking
    2.
    发明申请
    System and method for statistical design rule checking 有权
    统计设计规则检查的系统和方法

    公开(公告)号：US20060265674A1

    公开(公告)日：2006-11-23

    申请号：US11437600

    申请日：2006-05-19

    Applicant: Louis Scheffer

    Inventor： Louis Scheffer

    IPC: G06F17/50

    CPC classification number: G06F17/5081

    Abstract: Methods and systems for allowing an Integrated Circuit designer to specify one or more design rules, and to determine the expected probability of success of the IC design based on the design rules. Probability information is compiled for each circuit component, that specifies the probability of the circuit component working if a characteristic of the circuit component is varied. As the design rules are examined, the probability of each component working is calculated. The probabilities are combined to determine the overall probability of success for the IC design. Furthermore, the IC design may be broken into a plurality of portions, and design rules can be separately specified for each portion. This allows a designer the flexibility to use different design rules on different portions of the IC design.

    Abstract translation: 允许集成电路设计者指定一个或多个设计规则的方法和系统，并且基于设计规则确定IC设计成功的预期概率。 针对每个电路组件编制概率信息，其指定电路组件的特性如果变化时电路组件工作的概率。 随着设计规则的检验，每个部件工作的概率被计算出来。 将概率相结合以确定IC设计的成功概率。 此外，IC设计可以被分成多个部分，并且可以为每个部分分别指定设计规则。 这允许设计人员灵活地在IC设计的不同部分使用不同的设计规则。

    Method and apparatus for designing integrated circuit layouts
    3.
    发明申请
    Method and apparatus for designing integrated circuit layouts 失效
    设计集成电路布局的方法和装置

    公开(公告)号：US20050246674A1

    公开(公告)日：2005-11-03

    申请号：US10836581

    申请日：2004-05-01

    Applicant: Louis Scheffer

    Inventor： Louis Scheffer

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F17/5036

    Abstract: A method for modifying an IC layout using a library of pretabulated models, each model containing an environment with a feature, one or more geometries, and a modification to the feature that us calculated to produce a satisfactory feature on a wafer. The model may also contain a simulation of the environment reflecting no processing variations and/or a re-simulation of the environment reflecting one or more processing variations. The model may also contain data describing an electrical characteristic of the environment as a function of one or more process variations and/or describing an adjustment equation that uses geometry coverage percentages of particular areas in the layout to determine an adjustment to the modification. In some embodiments, and upper layer for an upper layer of an IC are modified using information (such as a density map) relating to a lower layout for a lower layer of the IC.

    Abstract translation: 一种使用预制模型库修改IC布局的方法，每个模型包含具有特征的环境，一个或多个几何形状，以及对我们计算的在晶片上产生令人满意的特征的特征的修改。 该模型还可以包含反映一种或多种处理变化的环境的模拟，该环境不反映处理变化和/或环境的再模拟。 该模型还可以包含描述作为一个或多个过程变化的函数的环境的电特性的数据和/或描述使用布局中特定区域的几何覆盖百分比来确定修改的调整的调整方程。 在一些实施例中，使用与IC的下层的较低布局相关的信息（例如密度图）来修改IC的上层的上层。

    Manufacturing Aware Deisgn and Design Aware Manufacturing
    7.
    发明申请
    Manufacturing Aware Deisgn and Design Aware Manufacturing 失效
    制造意识和设计意识制造

    公开(公告)号：US20060265679A1

    公开(公告)日：2006-11-23

    申请号：US11419495

    申请日：2006-05-20

    Applicant: Louis Scheffer ,  Akira Fujimura

    Inventor： Louis Scheffer ,  Akira Fujimura

    IPC: G06F17/50 ,  G06F19/00

    CPC classification number: G06F17/5068 ,  G03F7/70091 ,  G03F7/70125 ,  G03F7/70425 ,  G05B2219/35028 ,  G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    Abstract: Some embodiments of the invention provide a manufacturing aware process for designing an integrated circuit (“IC”) layout. The process receives a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC based on the IC layout. The process defines a set of design rules based on the specified manufacturing configuration. The process uses the set of design rules to design the IC layout. Some embodiments of the invention provide a design aware process for manufacturing an integrated circuit (“IC”). The process receives an IC design with an associated set of design properties. The process specifies a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture the IC, where the specified set of manufacturing settings are based on the set of design properties. The process manufactures the IC based on the manufacturing settings.

    Abstract translation: 本发明的一些实施例提供了一种用于设计集成电路（“IC”）布局的制造感知过程。 该过程接收制造配置，其指定用于基于IC布局来制造IC的一组机器的一组制造设置。 该过程基于指定的制造配置定义一组设计规则。 该过程使用一组设计规则来设计IC布局。 本发明的一些实施例提供了用于制造集成电路（“IC”）的设计感知过程。 该过程接收具有相关联的一组设计属性的IC设计。 该过程指定制造配置，其指定用于制造IC的一组机器的一组制造设置，其中指定的一组制造设置基于该组设计属性。 该过程基于制造设置制造IC。

    Method and System for Context-Specific Mask Writing
    9.
    发明申请
    Method and System for Context-Specific Mask Writing 失效
    上下文特定面具书写的方法和系统

    公开(公告)号：US20070266364A1

    公开(公告)日：2007-11-15

    申请号：US11781801

    申请日：2007-07-23

    Applicant: Robert Pack ,  Louis Scheffer

    Inventor： Robert Pack ,  Louis Scheffer

    IPC: G06F17/50

    CPC classification number: G03F1/68 ,  G03F1/36 ,  G03F1/78

    Abstract: A method for generating lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.

    Abstract translation: 一种用于产生光刻掩模的方法包括生成集成电路设计数据和使用来自集成电路设计数据的上下文信息来写入掩模。

    Method and system for incorporation of patterns and design rule checking
    10.
    发明申请
    Method and system for incorporation of patterns and design rule checking 有权
    结合模式和设计规则检查的方法和系统

    公开(公告)号：US20070006114A1

    公开(公告)日：2007-01-04

    申请号：US11437320

    申请日：2006-05-19

    Applicant: Louis Scheffer ,  David Noice

    Inventor： Louis Scheffer ,  David Noice

    IPC: G06F17/50

    CPC classification number: G06F17/5081

    Abstract: Methods and systems for representing the limitations of a lithographic process using a pattern library instead of, or in addition to, using design rules. The pattern library includes “known good” patterns, which chip fabricators know from experience are successful, and “known bad” patterns, which chip fabricators know to be unsuccessful. The pattern library can be used to contain exceptions to specified design rules, or to replace the design rules completely. In some implementations, the pattern library contains statistical information that is used to contribute to an overall figure of merit for the design. In other implementations, a routing tool may generate a plurality of possible IC layouts, and select one IC layout based on information contained in the pattern library.

    Abstract translation: 用于使用模式库代替使用设计规则或除了使用设计规则来表示光刻过程的限制的方法和系统。 模式库包括“已知的”模式，哪些芯片制造商从经验中知道是成功的，以及“已知的坏”模式，哪些芯片制造商知道是不成功的。 模式库可用于包含指定设计规则的异常，或者完全替换设计规则。 在一些实现中，模式库包含统计信息，用于为设计提供整体品质因数。 在其他实现中，路由工具可以生成多个可能的IC布局，并且基于包含在模式库中的信息来选择一个IC布局。

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