公开(公告)号：US20050246674A1

公开(公告)日：2005-11-03

申请号：US10836581

申请日：2004-05-01

Applicant: Louis Scheffer

Inventor： Louis Scheffer

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5036

Abstract: A method for modifying an IC layout using a library of pretabulated models, each model containing an environment with a feature, one or more geometries, and a modification to the feature that us calculated to produce a satisfactory feature on a wafer. The model may also contain a simulation of the environment reflecting no processing variations and/or a re-simulation of the environment reflecting one or more processing variations. The model may also contain data describing an electrical characteristic of the environment as a function of one or more process variations and/or describing an adjustment equation that uses geometry coverage percentages of particular areas in the layout to determine an adjustment to the modification. In some embodiments, and upper layer for an upper layer of an IC are modified using information (such as a density map) relating to a lower layout for a lower layer of the IC.

Abstract translation: 一种使用预制模型库修改IC布局的方法，每个模型包含具有特征的环境，一个或多个几何形状，以及对我们计算的在晶片上产生令人满意的特征的特征的修改。 该模型还可以包含反映一种或多种处理变化的环境的模拟，该环境不反映处理变化和/或环境的再模拟。 该模型还可以包含描述作为一个或多个过程变化的函数的环境的电特性的数据和/或描述使用布局中特定区域的几何覆盖百分比来确定修改的调整的调整方程。 在一些实施例中，使用与IC的下层的较低布局相关的信息（例如密度图）来修改IC的上层的上层。

公开(公告)号：US20070233419A1

公开(公告)日：2007-10-04

申请号：US11760715

申请日：2007-06-08

Applicant: Robert Pack ,  Louis Scheffer

Inventor： Robert Pack ,  Louis Scheffer

IPC: G06F19/00

CPC classification number: G03F1/84

Abstract: A method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to inspect a mask.

Abstract translation: 用于检查光刻掩模的方法包括生成集成电路设计数据并使用来自集成电路设计数据的上下文信息来检查掩模。

公开(公告)号：US20060265674A1

公开(公告)日：2006-11-23

申请号：US11437600

申请日：2006-05-19

Applicant: Louis Scheffer

Inventor： Louis Scheffer

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Methods and systems for allowing an Integrated Circuit designer to specify one or more design rules, and to determine the expected probability of success of the IC design based on the design rules. Probability information is compiled for each circuit component, that specifies the probability of the circuit component working if a characteristic of the circuit component is varied. As the design rules are examined, the probability of each component working is calculated. The probabilities are combined to determine the overall probability of success for the IC design. Furthermore, the IC design may be broken into a plurality of portions, and design rules can be separately specified for each portion. This allows a designer the flexibility to use different design rules on different portions of the IC design.

Abstract translation: 允许集成电路设计者指定一个或多个设计规则的方法和系统，并且基于设计规则确定IC设计成功的预期概率。 针对每个电路组件编制概率信息，其指定电路组件的特性如果变化时电路组件工作的概率。 随着设计规则的检验，每个部件工作的概率被计算出来。 将概率相结合以确定IC设计的成功概率。 此外，IC设计可以被分成多个部分，并且可以为每个部分分别指定设计规则。 这允许设计人员灵活地在IC设计的不同部分使用不同的设计规则。

公开(公告)号：US20070266364A1

公开(公告)日：2007-11-15

申请号：US11781801

申请日：2007-07-23

Applicant: Robert Pack ,  Louis Scheffer

Inventor： Robert Pack ,  Louis Scheffer

IPC: G06F17/50

CPC classification number: G03F1/68 ,  G03F1/36 ,  G03F1/78

Abstract: A method for generating lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.

Abstract translation: 一种用于产生光刻掩模的方法包括生成集成电路设计数据和使用来自集成电路设计数据的上下文信息来写入掩模。

公开(公告)号：US20070006114A1

公开(公告)日：2007-01-04

申请号：US11437320

申请日：2006-05-19

Applicant: Louis Scheffer ,  David Noice

Inventor： Louis Scheffer ,  David Noice

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Methods and systems for representing the limitations of a lithographic process using a pattern library instead of, or in addition to, using design rules. The pattern library includes “known good” patterns, which chip fabricators know from experience are successful, and “known bad” patterns, which chip fabricators know to be unsuccessful. The pattern library can be used to contain exceptions to specified design rules, or to replace the design rules completely. In some implementations, the pattern library contains statistical information that is used to contribute to an overall figure of merit for the design. In other implementations, a routing tool may generate a plurality of possible IC layouts, and select one IC layout based on information contained in the pattern library.

Abstract translation: 用于使用模式库代替使用设计规则或除了使用设计规则来表示光刻过程的限制的方法和系统。 模式库包括“已知的”模式，哪些芯片制造商从经验中知道是成功的，以及“已知的坏”模式，哪些芯片制造商知道是不成功的。 模式库可用于包含指定设计规则的异常，或者完全替换设计规则。 在一些实现中，模式库包含统计信息，用于为设计提供整体品质因数。 在其他实现中，路由工具可以生成多个可能的IC布局，并且基于包含在模式库中的信息来选择一个IC布局。

公开(公告)号：US20060265680A1

公开(公告)日：2006-11-23

申请号：US11437583

申请日：2006-05-19

Applicant: Louis Scheffer ,  Joel Phillips

Inventor： Louis Scheffer ,  Joel Phillips

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: An improved method, system, and computer program product is disclosed for predicting the geometric model of transistors once manufacturing and lithographic process effects are taken into consideration. This provides a much more accurate approach for modeling transistors since it is the actual expected geometric shapes that are analyzed, rather than an idealized model of the layout that does not accurately correspond to the actual manufactured IC product. The expected geometric shape includes systematic variations, which can be determined based on the layout, and the expected random variations, which can be determined based on the lithographic process.

公开(公告)号：US20060265677A1

公开(公告)日：2006-11-23

申请号：US11437794

申请日：2006-05-19

Applicant: Louis Scheffer ,  Wolfgang Staud ,  Judy Huckabay

Inventor： Louis Scheffer ,  Wolfgang Staud ,  Judy Huckabay

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: An improved method, system, and computer program product is disclosed for increased accuracy for extraction of electrical parameters of an IC design. Extraction is performed upon the expected geometric model of the printed layout once manufacturing and lithographic process effects are taken into consideration. This provides a much more accurate approach for performing extraction since it is the actual expected geometric shapes that are analyzed, rather than an idealized model of the layout that does not accurately correspond to the actual manufactured IC product. The extracted electrical parameters are checked for acceptability. If not acceptable, then the IC design can be modified to address any identified problems or desired improvements to the design.

Abstract translation: 公开了一种改进的方法，系统和计算机程序产品，用于提高IC设计的电参数的精度。 一旦制造和平版印刷过程效果被考虑，就按照打印布局的预期几何模型进行提取。 这提供了一种更精确的执行提取方法，因为它是被分析的实际预期几何形状，而不是不能准确对应于实际制造的IC产品的理想化模型。 检查提取的电气参数是否可接受。 如果不能接受，则可以修改IC设计以解决任何已识别的问题或对设计的期望改进。

公开(公告)号：US20050246675A1

公开(公告)日：2005-11-03

申请号：US10836582

申请日：2004-05-01

Applicant: Louis Scheffer

Inventor： Louis Scheffer

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method for modifying an upper layout for an upper layer of an IC using information of a lower layout for a lower layer of the IC, the method including 1) receiving the upper layout containing features and modifications to features, 2) producing a density map of the lower layout having geometry coverages of sub-regions of the lower layout, 4) selecting a feature in the upper layout, 5) retrieving, from the density map, the geometry coverage of a sub-region below the feature, 6) determining a vertical deviation of the feature using the geometry coverage, 7) determining an alteration to the modification using the vertical deviation, 8) applying the alteration to the modification, and 9) repeating for all features. In some embodiments, the upper layout is designed using a library of pretabulated models, each model containing a modification to a feature calculated to produce a satisfactory feature on a wafer.

Abstract translation: 一种用于使用用于IC的下层的下部布局的信息来修改IC的上层布局的方法，所述方法包括：1）接收包含特征的上部布局和对特征的修改，2）产生密度图 下部布局具有下部布局的子区域的几何覆盖，4）在上部布局中选择特征，5）从密度图中检索特征下方的子区域的几何覆盖，6）确定 使用几何覆盖的特征的垂直偏差，7）使用垂直偏差确定对修改的改变，8）将修改应用于修改，以及9）针对所有特征重复。 在一些实施例中，使用预制模型库设计上部布局，每个模型包含被计算以在晶片上产生令人满意的特征的特征的修改。

公开(公告)号：US20050216877A1

公开(公告)日：2005-09-29

申请号：US11143361

申请日：2005-06-01

Applicant: Robert Pack ,  Louis Scheffer

Inventor： Robert Pack ,  Louis Scheffer

IPC: G03F9/00 ,  G06F17/50

CPC classification number: G03F1/68 ,  G03F1/36 ,  G03F1/78

Abstract: A method for generating lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask.

Abstract translation: 一种用于产生光刻掩模的方法包括产生集成电路设计数据和使用来自集成电路设计数据的上下文信息来写入掩模。

公开(公告)号：US08117566B2

公开(公告)日：2012-02-14

申请号：US12276267

申请日：2008-11-21

Applicant: Louis Scheffer

Inventor： Louis Scheffer

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/10

Abstract: A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed.

Abstract translation: 公开了一种将制造意识压缩成小表示并使路由器能够参与表示而不执行或理解详细过程分析的机制。