发明授权
US08125253B2 System and method for dynamically switching between low and high frequency reference clock to PLL and minimizing PLL output frequency changes
有权
用于在低频和高频参考时钟之间动态切换到PLL并最小化PLL输出频率变化的系统和方法
- 专利标题： System and method for dynamically switching between low and high frequency reference clock to PLL and minimizing PLL output frequency changes
- 专利标题（中）： 用于在低频和高频参考时钟之间动态切换到PLL并最小化PLL输出频率变化的系统和方法
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申请号： US12610438申请日： 2009-11-02
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公开(公告)号： US08125253B2公开(公告)日： 2012-02-28
- 发明人: Stanley Goldman , Srinath Ramaswamy
- 申请人： Stanley Goldman , Srinath Ramaswamy
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 John R. Pessetto; W. James Brady; Frederick J. Telecky, Jr.
- 主分类号： H03L7/06
- IPC分类号： H03L7/06
摘要：
A circuit is provided for use with a clock having an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter portion and a voltage controlled oscillator portion. The input divider portion receives a reference signal and outputs a divided reference signal. The feedback divider portion receives an output signal from the circuit and outputs a divided feedback signal. The phase detector portion outputs a phase detector signal based on the divided reference signal and the divided feedback signal. The loop compensation filter portion outputs a tuning signal based on the phase detector signal. The voltage controlled oscillator portion output the outputs a signal based on the tuning signal. The phase detector portion changes the phase detector signal based on the input divider portion receiving the control signal and the feedback divider portion receiving the control signal.
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