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    SYSTEM AND METHOD FOR DYNAMICALLY SWITCHING BETWEEN LOW AND HIGH FREQUENCY REFERENCE CLOCK TO PLL AND MINIMIZING PLL OUTPUT FREQUENCY CHANGES
    1.
    发明申请
    SYSTEM AND METHOD FOR DYNAMICALLY SWITCHING BETWEEN LOW AND HIGH FREQUENCY REFERENCE CLOCK TO PLL AND MINIMIZING PLL OUTPUT FREQUENCY CHANGES 有权
    低频和高频参考时钟之间的动态切换到PLL和最小化PLL输出频率变化的系统和方法

    公开(公告)号：US20110102030A1

    公开(公告)日：2011-05-05

    申请号：US12610438

    申请日：2009-11-02

    申请人： Stanley Goldman ,  Srinath Ramaswamy

    发明人： Stanley Goldman ,  Srinath Ramaswamy

    IPC分类号： H03L7/06

    CPC分类号： H03L7/193 ,  H03L7/093

    摘要： A circuit is provided for use with a clock signal having a plurality of clock pulses, each clock pulse having a rising edge and a falling edge. The circuit is operable to receive a reference signal and to output an output signal. The circuit includes an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter portion and a voltage controlled oscillator portion. The input divider portion is arranged to receive the reference signal and is operable to output a divided reference signal. The feedback divider portion is arranged to receive the output signal and is operable to output a divided feedback signal. The phase detector portion is operable to output a phase detector signal based on the divided reference signal and the divided feedback signal. The loop compensation filter portion is operable to output a tuning signal based on the phase detector signal. The voltage controlled oscillator portion is operable to output the output signal based on the tuning signal. The phase detector portion is further operable to change the phase detector signal based on the input divider portion receiving the control signal and the feedback divider portion receiving the control signal, and further based on the control signal and a rising edge of a clock pulse.

    摘要翻译： 提供电路用于具有多个时钟脉冲的时钟信号，每个时钟脉冲具有上升沿和下降沿。 电路可操作以接收参考信号并输出​​输出信号。 电路包括输入分频器部分，反馈分频器部分，相位检测器部分，环路补偿滤波器部分和压控振荡器部分。 输入分频器部分被布置成接收参考信号并且可操作以输出分频的参考信号。 反馈分配器部分被布置成接收输出信号并且可操作以输出分离的反馈信号。 相位检测器部分可操作以基于划分的参考信号和分频反馈信号输出相位检测器信号。 环路补偿滤波器部分可操作以基于相位检测器信号输出调谐信号。 压控振荡器部分可操作以基于调谐信号输出输出信号。 相位检测器部分还可操作以基于接收控制信号的输入分频器部分和接收控制信号的反馈分频器部分，并且还基于控制信号和时钟脉冲的上升沿来改变相位检测器信号。

    System and method for dynamically switching between low and high frequency reference clock to PLL and minimizing PLL output frequency changes
    2.
    发明授权
    System and method for dynamically switching between low and high frequency reference clock to PLL and minimizing PLL output frequency changes 有权
    用于在低频和高频参考时钟之间动态切换到PLL并最小化PLL输出频率变化的系统和方法

    公开(公告)号：US08125253B2

    公开(公告)日：2012-02-28

    申请号：US12610438

    申请日：2009-11-02

    申请人： Stanley Goldman ,  Srinath Ramaswamy

    发明人： Stanley Goldman ,  Srinath Ramaswamy

    IPC分类号： H03L7/06

    CPC分类号： H03L7/193 ,  H03L7/093

    摘要： A circuit is provided for use with a clock having an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter portion and a voltage controlled oscillator portion. The input divider portion receives a reference signal and outputs a divided reference signal. The feedback divider portion receives an output signal from the circuit and outputs a divided feedback signal. The phase detector portion outputs a phase detector signal based on the divided reference signal and the divided feedback signal. The loop compensation filter portion outputs a tuning signal based on the phase detector signal. The voltage controlled oscillator portion output the outputs a signal based on the tuning signal. The phase detector portion changes the phase detector signal based on the input divider portion receiving the control signal and the feedback divider portion receiving the control signal.

    摘要翻译： 提供了一种与具有输入分频器部分，反馈分频器部分，相位检测器部分，环路补偿滤波器部分和压控振荡器部分的时钟一起使用的电路。 输入分频器部分接收参考信号并输出​​分频的参考信号。 反馈分配器部分接收来自电路的输出信号并输出​​分频的反馈信号。 相位检测器部分基于划分的参考信号和分离的反馈信号输出相位检测器信号。 环路补偿滤波器部分基于相位检测器信号输出调谐信号。 压控振荡器部分输出基于调谐信号的信号。 相位检测器部分基于接收控制信号的输入分频器部分和接收控制信号的反馈分频器部分来改变相位检测器信号。

    CROSS-LOOP ANTENNA
    3.
    发明申请
    CROSS-LOOP ANTENNA 审中-公开
    交叉天线

    公开(公告)号：US20130026586A1

    公开(公告)日：2013-01-31

    申请号：US13191157

    申请日：2011-07-26

    申请人： Eunyoung Seok ,  Srinath Ramaswamy ,  Brian P. Ginsburg ,  Vijay B. Rentala ,  Baher Haroun

    发明人： Eunyoung Seok ,  Srinath Ramaswamy ,  Brian P. Ginsburg ,  Vijay B. Rentala ,  Baher Haroun

    IPC分类号： H01L31/115 ,  H05K1/11 ,  H05K1/00

    CPC分类号： H01L31/08 ,  H01L2224/73204 ,  H05K3/3436 ,  H05K2201/10098

    摘要： An antenna is provided. This antenna is contained within a package that is secured to an IC (which allows radiation to propagated away for a printed circuit board so as to reduce interference), and this antenna includes two loop antennas that are shorted to ground and that “overlap” and includes a “via wall.” With this configuration, circular polarization can be achieved by varying the relative phases of the input signals, and the “via wall” improves efficiency by reducing surface waves.

    摘要翻译： 提供天线。 该天线被包含在固定到IC（其允许辐射传播到印刷电路板以便减少干扰）的封装内，并且该天线包括两个短路到地的环形天线，并且重叠并且包括一个 通过墙。 通过这种配置，可以通过改变输入信号的相对相位来实现圆偏振，并且通孔减小表面波来提高效率。

    Class-D amplifier system
    7.
    发明申请
    Class-D amplifier system 有权
    D类放大器系统

    公开(公告)号：US20070024365A1

    公开(公告)日：2007-02-01

    申请号：US11193867

    申请日：2005-07-29

    申请人： Srinath Ramaswamy ,  Jagadeesh Krishnan ,  Gangadhar Burra

    发明人： Srinath Ramaswamy ,  Jagadeesh Krishnan ,  Gangadhar Burra

    IPC分类号： H03F3/217

    CPC分类号： H03F3/217 ,  H03F1/30 ,  H03F1/34 ,  H03F3/2173 ,  H03F2200/261 ,  H03F2200/331 ,  H03F2200/351

    摘要： A Class-D amplifier system may include an input stage that includes an Nth order filter, where N>1. The input stage filters an input signal to provide a filtered output signal, an input of the input stage being configured to receive the input signal as a digital pulse-width-modulated (PWM) signal. A comparator provides a quantized output signal based on the filtered output signal. An output stage is connected between a first voltage rail and a second voltage rail. The output stage provides a switching output signal at an output that varies between the first voltage rail and the second voltage rail based on the quantized output signal. A feedback path connects the output of the output stage with the input of the input stage, such that the Nth order filter compensates for variations in at least one of the first voltage rail and the second voltage rail.

    摘要翻译： D类放大器系统可以包括输入级，该输入级包括N≥1级的N次级滤波器。 输入级对输入信号进行滤波以提供经滤波的输出信号，输入级的输入被配置为接收输入信号作为数字脉宽调制（PWM）信号。 比较器基于滤波的输出信号提供量化的输出信号。 输出级连接在第一电压轨和第二电压轨之间。 输出级基于量化的输出信号在输出端提供在第一电压轨和第二电压轨之间变化的开关输出信号。 反馈路径将输出级的输出与输入级的输入相连，使得第N级阶滤波器补偿第一电压轨和第二电压轨中的至少一个的变化。

    Systems for pseudo-BD modulation
    8.
    发明申请
    Systems for pseudo-BD modulation 有权
    伪BD调制系统

    公开(公告)号：US20070024361A1

    公开(公告)日：2007-02-01

    申请号：US11193871

    申请日：2005-07-29

    申请人： Jagadeesh Krishnan ,  Srinath Ramaswamy ,  Gangadhar Burra

    发明人： Jagadeesh Krishnan ,  Srinath Ramaswamy ,  Gangadhar Burra

    IPC分类号： H03F3/28

    CPC分类号： H03F3/68 ,  H03F3/2173 ,  H03F2200/165 ,  H03F2200/351 ,  H03F2200/459

    摘要： An amplifier system in accordance with an aspect of the present invention comprises a switching amplifier that drives a load with a pulse-width modulated (PWM) output signal that varies between first and second rails based on a first control input signal, and a common mode supply that provides a switching signal that varies between third and fourth rails to maintain a common mode voltage of the load at a level that is between the first and second rails.

    摘要翻译： 根据本发明的一个方面的放大器系统包括开关放大器，其基于第一控制输入信号和第二控制输入信号在第一和第二轨道之间变化的脉冲宽度调制（PWM）输出信号驱动负载， 电源提供在第三和第四导轨之间变化的开关信号，以将负载的共模电压维持在第一和第二导轨之间的水平。

    ROUTING FOR A PACKAGE ANTENNA
    9.
    发明申请
    ROUTING FOR A PACKAGE ANTENNA 有权
    套装天线的路由

    公开(公告)号：US20130059551A1

    公开(公告)日：2013-03-07

    申请号：US13227254

    申请日：2011-09-07

    申请人： Brian P. Ginsburg ,  Eunyoung Seok ,  Vijay B. Rentala ,  Srinath Ramaswamy ,  Baher Haroun

    发明人： Brian P. Ginsburg ,  Eunyoung Seok ,  Vijay B. Rentala ,  Srinath Ramaswamy ,  Baher Haroun

    IPC分类号： H04B1/44

    CPC分类号： H04B1/44 ,  H01L23/49816 ,  H01L23/66 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/14 ,  H01L2924/15321 ,  H01Q21/0006 ,  H01Q21/061 ,  H01Q23/00 ,  H01L2924/00012

    摘要： An apparatus is provided. A plurality of transceiver antennas are arranged to form a phased array, where each antenna include a differential transmit antenna and a differential receive antenna arranged in a first pattern. A plurality of transceivers are arranged in a second pattern that is substantially symmetrical, and each transceiver is associated with at least one of the transceiver antennas and includes a feed network. Each feed network has a power amplifier (PA), a first matching network that is coupled between the PA and its associated transmit antenna so as to translate the phase of each differential transmit signal, a low noise amplifier (LNA), and a second matching network that is coupled between the LNA and its associated receive antenna so as to translate the phase of each differential receive signal.

    摘要翻译： 提供了一种装置。 多个收发天线被布置成形成相控阵列，其中每个天线包括以第一模式布置的差分发射天线和差分接收天线。 多个收发器以基本上对称的第二图案布置，并且每个收发器与至少一个收发器天线相关联并且包括馈送网络。 每个馈送网络具有功率放大器（PA），第一匹配网络耦合在PA与其相关联的发射天线之间，以便平移每个差分发射信号的相位，低噪声放大器（LNA）和第二匹配 网络，其耦合在LNA及其相关联的接收天线之间，以便平移每个差分接收信号的相位。