In a system, a memory bus has a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch to selectively couple and decouple the first bus segment and the second bus segment in response to control information from the control logic. Note that the control logic may output control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in an electrical length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to effect another change in the electrical length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate.