公开(公告)号：US08135890B2

公开(公告)日：2012-03-13

申请号：US12428114

申请日：2009-04-22

Applicant: Steven C. Woo ,  Scott C. Best

Inventor： Steven C. Woo ,  Scott C. Best

IPC: G06F13/00

CPC classification number: E04B2/58 ,  E04B1/24 ,  E04C2/423 ,  G06F13/4243

Abstract: In a system, a memory bus has a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch to selectively couple and decouple the first bus segment and the second bus segment in response to control information from the control logic. Note that the control logic may output control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in an electrical length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to effect another change in the electrical length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate.

Abstract translation: 在系统中，存储器总线具有耦合到存储器控制器的第一总线段，存储器控制器包括控制逻辑和第一存储器件，耦合到第二存储器件的第二总线段以及用于选择性地耦合和去耦合第一总线段 以及响应于来自控制逻辑的控制信息的第二总线段。 注意，控制逻辑可以将控制信息输出到开关以选择性地去耦合第一总线段和第二总线段以实现存储器总线的电长度的改变，以使得能够在第一存储器装置相对于第一存储器件进行数据传送 数据速率。 另外，控制逻辑可以将控制信息输出到开关以选择性地耦合第一总线段和第二总线段，以实现存储器总线的电长度的另一变化，以使得能够在第二存储器装置相对于第二存储器件进行数据传送 数据速率比第一个数据速率慢。

公开(公告)号：US08332556B2

公开(公告)日：2012-12-11

申请号：US13349210

申请日：2012-01-12

Applicant: Steven C. Woo ,  Scott C. Best

Inventor： Steven C. Woo ,  Scott C. Best

IPC: G06F13/00

CPC classification number: E04B2/58 ,  E04B1/24 ,  E04C2/423 ,  G06F13/4243

Abstract: A memory bus with a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch between the first bus segment and the second bus segment. The control logic outputs control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in the length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to increase the length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate.

Abstract translation: 存储器总线，其具有耦合到存储器控制器的第一总线段，存储器控制器包括控制逻辑和第一存储器件，耦合到第二存储器件的第二总线段以及第一总线段和第二总线段之间的开关。 控制逻辑将控制信息输出到开关以选择性地分离第一总线段和第二总线段以实现存储器总线的长度的改变，以使得能够以第一数据速率相对于第一存储器件的数据传输。 另外，控制逻辑可以将控制信息输出到开关以选择性地耦合第一总线段和第二总线段以增加存储器总线的长度，以使得能够以第二数据速率相对于第二存储器设备进行数据传输， 比第一个数据速率慢。

公开(公告)号：US20120110229A1

公开(公告)日：2012-05-03

申请号：US13349210

申请日：2012-01-12

Applicant: Steven C. Woo ,  Scott C. Best

Inventor： Steven C. Woo ,  Scott C. Best

IPC: G06F13/42

CPC classification number: E04B2/58 ,  E04B1/24 ,  E04C2/423 ,  G06F13/4243

Abstract: A memory bus with a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch between the first bus segment and the second bus segment. The control logic outputs control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in the length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to increase the length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate.

Abstract translation: 存储器总线，其具有耦合到存储器控制器的第一总线段，存储器控制器包括控制逻辑和第一存储器件，耦合到第二存储器件的第二总线段以及第一总线段和第二总线段之间的开关。 控制逻辑将控制信息输出到开关以选择性地分离第一总线段和第二总线段以实现存储器总线的长度的改变，以使得能够以第一数据速率相对于第一存储器件的数据传输。 另外，控制逻辑可以将控制信息输出到开关以选择性地耦合第一总线段和第二总线段以增加存储器总线的长度，以使得能够以第二数据速率相对于第二存储器设备进行数据传输， 比第一个数据速率慢。

公开(公告)号：US20090300260A1

公开(公告)日：2009-12-03

申请号：US12428114

申请日：2009-04-22

Applicant: Steven C. Woo ,  Scott C. Best

Inventor： Steven C. Woo ,  Scott C. Best

IPC: G06F13/00 ,  G06F12/06

CPC classification number: E04B2/58 ,  E04B1/24 ,  E04C2/423 ,  G06F13/4243

Abstract: In a system, a memory bus has a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch to selectively couple and decouple the first bus segment and the second bus segment in response to control information from the control logic. Note that the control logic may output control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in an electrical length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to effect another change in the electrical length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate.

Abstract translation: 在系统中，存储器总线具有耦合到存储器控制器的第一总线段，存储器控制器包括控制逻辑和第一存储器件，耦合到第二存储器件的第二总线段以及用于选择性地耦合和去耦合第一总线段 以及响应于来自控制逻辑的控制信息的第二总线段。 注意，控制逻辑可以将控制信息输出到开关以选择性地去耦合第一总线段和第二总线段以实现存储器总线的电长度的改变，以使得能够在第一存储器装置相对于第一存储器件进行数据传送 数据速率。 另外，控制逻辑可以将控制信息输出到开关以选择性地耦合第一总线段和第二总线段，以实现存储器总线的电长度的另一变化，以使得能够在第二存储器装置相对于第二存储器件进行数据传送 数据速率比第一个数据速率慢。

公开(公告)号：US08407441B2

公开(公告)日：2013-03-26

申请号：US13111446

申请日：2011-05-19

Applicant: Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G06F12/00

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

公开(公告)号：US08018789B2

公开(公告)日：2011-09-13

申请号：US12557361

申请日：2009-09-10

Applicant: Steven C. Woo ,  Craig E. Hampel

Inventor： Steven C. Woo ,  Craig E. Hampel

IPC: G11C5/14

CPC classification number: G11C5/02

Abstract: The memory module includes front and back faces. Multiple devices are disposed on each of the faces. A first control line serially connects a first group of devices on both the front and back faces so that the first group of devices commonly contribute multiple bits to a data bus. A second control line serially connects a second group of devices on both the front and back faces so that the second group of devices commonly contribute multiple bits to a data bus.

Abstract translation: 内存模块包括前面和后面。 在每个面上设置多个装置。 第一控制线串联连接前面和后表面上的第一组设备，使得第一组设备通常向数据总线贡献多个位。 第二控制线串联连接前面和后表面上的第二组设备，使得第二组设备通常向数据总线贡献多个位。

公开(公告)号：US06742097B2

公开(公告)日：2004-05-25

申请号：US09919373

申请日：2001-07-30

Applicant: Steven C. Woo ,  Pradeep Batra

Inventor： Steven C. Woo ,  Pradeep Batra

IPC: G06F1200

CPC classification number: G06F12/0292 ,  G06F12/023 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A memory system includes physical memory devices or ranks of memory devices that can be set to reduced power modes. In one embodiment, a hardware memory controller receives memory instructions in terms of a logical address space. In response to the relative usages of different addresses within the logical address space, the memory controller maps the logical address space to physical memory in a way that reduces the number of memory devices that are being used. Other memory devices are then set to reduced power modes. In another embodiment, an operating system maintains a free page list indicating portions of physical memory that are not currently allocated. The operating system periodically sorts this list by group, where each group corresponds to a set or rank of memory devices. The groups are sorted in order from those receiving the heaviest usage to those receiving the lightest usage. When allocating memory, the memory is allocated from the sorted page list so that memory is preferentially allocated from those memory devices that are already receiving the highest usage.

公开(公告)号：US6021076A

公开(公告)日：2000-02-01

申请号：US118696

申请日：1998-07-16

Applicant: Steven C. Woo ,  Ramprasad Satagopan ,  Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel

Inventor： Steven C. Woo ,  Ramprasad Satagopan ,  Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel

IPC: G06F1/20 ,  G06F1/32 ,  G11C7/04 ,  G11C11/406

CPC classification number: G06F1/3225 ,  G06F1/206 ,  G11C11/406 ,  G11C11/40626 ,  Y02B60/1275

Abstract: A memory system configured to provide thermal regulation of a plurality of memory devices is disclosed. The memory system comprises a memory device coupled to a bus. Additionally, the memory system also comprises a controller coupled to the bus. The controller determines an operating temperature of the memory device. Based on the operating temperature of the memory device, the controller is further operable to manipulate the operation of the memory system.

Abstract translation: 公开了一种被配置为提供多个存储器件的热调节的存储器系统。 存储器系统包括耦合到总线的存储器件。 此外，存储器系统还包括耦合到总线的控制器。 控制器确定存储器件的工作温度。 基于存储器件的操作温度，控制器还可操作以操纵存储器系统的操作。

公开(公告)号：US07370152B2

公开(公告)日：2008-05-06

申请号：US10881413

申请日：2004-06-29

Applicant: Steven C. Woo ,  Bradley A. May ,  Liewei Bao

Inventor： Steven C. Woo ,  Bradley A. May ,  Liewei Bao

IPC: G06F12/00

CPC classification number: G06F13/1642 ,  G06F12/0862 ,  G06F2212/6022

Abstract: A memory controller monitors requests from one or more computer subsystems and issues one or more prefetch commands if the memory controller detects that the memory system is idle after a period of activity, or if a prefetch buffer read hit occurs. In some embodiments, results of a prefetching operations are stored in a prefetch buffer configured to provide an automatic aging mechanism, which evicts prefetched data from time to time. The prefetched data in the prefetch buffer is released and sent back to the requester in order with respect to previous memory access requests.

Abstract translation: 如果存储器控制器在一段活动之后检测到存储器系统空闲，或者如果发生预取缓冲器读取命中，则存储器控制器监视来自一个或多个计算机子系统的请求并发出一个或多个预取命令。 在一些实施例中，预取操作的结果被存储在预取缓冲器中，该预取缓冲器被配置为提供自动老化机制，其不时地推移预取的数据。 预取缓冲器中的预取数据被释放，并相对于先前的存储器访问请求被发送回请求者。

公开(公告)号：US07003639B2

公开(公告)日：2006-02-21

申请号：US10873670

申请日：2004-06-21

Applicant: Ely K. Tsern ,  Ramprasad Satagopan ,  Richard M. Barth ,  Steven C. Woo

Inventor： Ely K. Tsern ,  Ramprasad Satagopan ,  Richard M. Barth ,  Steven C. Woo

IPC: G06F12/00

CPC classification number: G06F1/3275 ,  G06F1/3203 ,  G06F12/0215 ,  G06F2212/1028 ,  G11C11/4074 ,  Y02D10/13 ,  Y02D10/14

Abstract: A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal. Command issue circuitry issues power state commands and access commands to the dynamic memory devices in accordance with the at least one command selection signal and the address in the memory access request.