公开(公告)号：US08407441B2

公开(公告)日：2013-03-26

申请号：US13111446

申请日：2011-05-19

Applicant: Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G06F12/00

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

公开(公告)号：US08135890B2

公开(公告)日：2012-03-13

申请号：US12428114

申请日：2009-04-22

Applicant: Steven C. Woo ,  Scott C. Best

Inventor： Steven C. Woo ,  Scott C. Best

IPC: G06F13/00

CPC classification number: E04B2/58 ,  E04B1/24 ,  E04C2/423 ,  G06F13/4243

Abstract: In a system, a memory bus has a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch to selectively couple and decouple the first bus segment and the second bus segment in response to control information from the control logic. Note that the control logic may output control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in an electrical length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to effect another change in the electrical length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate.

Abstract translation: 在系统中，存储器总线具有耦合到存储器控制器的第一总线段，存储器控制器包括控制逻辑和第一存储器件，耦合到第二存储器件的第二总线段以及用于选择性地耦合和去耦合第一总线段 以及响应于来自控制逻辑的控制信息的第二总线段。 注意，控制逻辑可以将控制信息输出到开关以选择性地去耦合第一总线段和第二总线段以实现存储器总线的电长度的改变，以使得能够在第一存储器装置相对于第一存储器件进行数据传送 数据速率。 另外，控制逻辑可以将控制信息输出到开关以选择性地耦合第一总线段和第二总线段，以实现存储器总线的电长度的另一变化，以使得能够在第二存储器装置相对于第二存储器件进行数据传送 数据速率比第一个数据速率慢。

公开(公告)号：US08018789B2

公开(公告)日：2011-09-13

申请号：US12557361

申请日：2009-09-10

Applicant: Steven C. Woo ,  Craig E. Hampel

Inventor： Steven C. Woo ,  Craig E. Hampel

IPC: G11C5/14

CPC classification number: G11C5/02

Abstract: The memory module includes front and back faces. Multiple devices are disposed on each of the faces. A first control line serially connects a first group of devices on both the front and back faces so that the first group of devices commonly contribute multiple bits to a data bus. A second control line serially connects a second group of devices on both the front and back faces so that the second group of devices commonly contribute multiple bits to a data bus.

Abstract translation: 内存模块包括前面和后面。 在每个面上设置多个装置。 第一控制线串联连接前面和后表面上的第一组设备，使得第一组设备通常向数据总线贡献多个位。 第二控制线串联连接前面和后表面上的第二组设备，使得第二组设备通常向数据总线贡献多个位。

公开(公告)号：US06742097B2

公开(公告)日：2004-05-25

申请号：US09919373

申请日：2001-07-30

Applicant: Steven C. Woo ,  Pradeep Batra

Inventor： Steven C. Woo ,  Pradeep Batra

IPC: G06F1200

CPC classification number: G06F12/0292 ,  G06F12/023 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A memory system includes physical memory devices or ranks of memory devices that can be set to reduced power modes. In one embodiment, a hardware memory controller receives memory instructions in terms of a logical address space. In response to the relative usages of different addresses within the logical address space, the memory controller maps the logical address space to physical memory in a way that reduces the number of memory devices that are being used. Other memory devices are then set to reduced power modes. In another embodiment, an operating system maintains a free page list indicating portions of physical memory that are not currently allocated. The operating system periodically sorts this list by group, where each group corresponds to a set or rank of memory devices. The groups are sorted in order from those receiving the heaviest usage to those receiving the lightest usage. When allocating memory, the memory is allocated from the sorted page list so that memory is preferentially allocated from those memory devices that are already receiving the highest usage.

公开(公告)号：US6021076A

公开(公告)日：2000-02-01

申请号：US118696

申请日：1998-07-16

Applicant: Steven C. Woo ,  Ramprasad Satagopan ,  Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel

Inventor： Steven C. Woo ,  Ramprasad Satagopan ,  Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel

IPC: G06F1/20 ,  G06F1/32 ,  G11C7/04 ,  G11C11/406

CPC classification number: G06F1/3225 ,  G06F1/206 ,  G11C11/406 ,  G11C11/40626 ,  Y02B60/1275

Abstract: A memory system configured to provide thermal regulation of a plurality of memory devices is disclosed. The memory system comprises a memory device coupled to a bus. Additionally, the memory system also comprises a controller coupled to the bus. The controller determines an operating temperature of the memory device. Based on the operating temperature of the memory device, the controller is further operable to manipulate the operation of the memory system.

Abstract translation: 公开了一种被配置为提供多个存储器件的热调节的存储器系统。 存储器系统包括耦合到总线的存储器件。 此外，存储器系统还包括耦合到总线的控制器。 控制器确定存储器件的工作温度。 基于存储器件的操作温度，控制器还可操作以操纵存储器系统的操作。

公开(公告)号：US09142281B1

公开(公告)日：2015-09-22

申请号：US14698755

申请日：2015-04-28

Applicant: Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G06F12/00 ,  G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G06F12/06

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

公开(公告)号：US20120278583A1

公开(公告)日：2012-11-01

申请号：US13500067

申请日：2010-11-10

Applicant: Steven C. Woo ,  Trung A. Diep ,  Michael T. Ching

Inventor： Steven C. Woo ,  Trung A. Diep ,  Michael T. Ching

IPC: G06F12/00

CPC classification number: G06F13/1652 ,  G06F9/5016 ,  G06F9/52

Abstract: The disclosed embodiments relate to a system for processing memory references received from multiple processor cores. During operation, the system monitors the memory references to determine whether memory references from different processor cores are interfering with each other as the memory references are processed by a memory system. If memory references from different processor cores are interfering with each other, the system time-multiplexes the processing of memory references between processor cores, so that a block of consecutive memory references from a given processor core is processed by the memory system before memory references from other processor cores are processed.

Abstract translation: 所公开的实施例涉及用于处理从多个处理器核心接收的存储器参考的系统。 在操作期间，系统监视存储器引用以确定来自不同处理器核的存储器引用是否因存储器引用被存储器系统处理而彼此干扰。 如果来自不同处理器核心的存储器引用彼此干扰，则系统对处理器内核之间的存储器引用进行时间复用，从而在存储器引用之前由存储器系统处理来自给定处理器内核的连续存储器引用块 处理其他处理器内核。

公开(公告)号：US08184497B2

公开(公告)日：2012-05-22

申请号：US13224251

申请日：2011-09-01

Applicant: Steven C. Woo ,  Craig E. Hampel

Inventor： Steven C. Woo ,  Craig E. Hampel

IPC: G11C5/14

CPC classification number: G11C5/02

Abstract: The memory module includes front and back faces. Multiple devices are disposed on each of the faces. A first control line serially connects a first group of devices on both the front and back faces so that the first group of devices commonly contribute multiple bits to a data bus. A second control line serially connects a second group of devices on both the front and back faces so that the second group of devices commonly contribute multiple bits to a data bus.

Abstract translation: 内存模块包括前面和后面。 在每个面上设置多个装置。 第一控制线串联连接前面和后表面上的第一组设备，使得第一组设备通常向数据总线贡献多个位。 第二控制线串联连接前面和后表面上的第二组设备，使得第二组设备通常向数据总线贡献多个位。

公开(公告)号：US20090300260A1

公开(公告)日：2009-12-03

申请号：US12428114

申请日：2009-04-22

Applicant: Steven C. Woo ,  Scott C. Best

Inventor： Steven C. Woo ,  Scott C. Best

IPC: G06F13/00 ,  G06F12/06

CPC classification number: E04B2/58 ,  E04B1/24 ,  E04C2/423 ,  G06F13/4243

Abstract: In a system, a memory bus has a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch to selectively couple and decouple the first bus segment and the second bus segment in response to control information from the control logic. Note that the control logic may output control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in an electrical length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to effect another change in the electrical length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate.

Abstract translation: 在系统中，存储器总线具有耦合到存储器控制器的第一总线段，存储器控制器包括控制逻辑和第一存储器件，耦合到第二存储器件的第二总线段以及用于选择性地耦合和去耦合第一总线段 以及响应于来自控制逻辑的控制信息的第二总线段。 注意，控制逻辑可以将控制信息输出到开关以选择性地去耦合第一总线段和第二总线段以实现存储器总线的电长度的改变，以使得能够在第一存储器装置相对于第一存储器件进行数据传送 数据速率。 另外，控制逻辑可以将控制信息输出到开关以选择性地耦合第一总线段和第二总线段，以实现存储器总线的电长度的另一变化，以使得能够在第二存储器装置相对于第二存储器件进行数据传送 数据速率比第一个数据速率慢。

公开(公告)号：US06954837B2

公开(公告)日：2005-10-11

申请号：US10823115

申请日：2004-04-12

Applicant: Steven C. Woo ,  Pradeep Batra

Inventor： Steven C. Woo ,  Pradeep Batra

IPC: G06F12/02 ,  G06F12/00

CPC classification number: G06F12/0292 ,  G06F12/023 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A memory system includes physical memory devices or ranks of memory devices that can be set to reduced power modes. In one embodiment, a hardware memory controller receives memory instructions in terms of a logical address space. In response to the relative usages of different addresses within the logical address space, the memory controller maps the logical address space to physical memory in a way that reduces the number of memory devices that are being used. Other memory devices are then set to reduced power modes. In another embodiment, an operating system maintains a free page list indicating portions of physical memory that are not currently allocated. The operating system periodically sorts this list by group, where each group corresponds to a set or rank of memory devices. The groups are sorted in order from those receiving the heaviest usage to those receiving the lightest usage. When allocating memory, the memory is allocated from the sorted page list so that memory is preferentially allocated from those memory devices that are already receiving the highest usage.

Abstract translation: 存储器系统包括可以被设置为降低功率模式的物理存储器件或存储器件的等级。 在一个实施例中，硬件存储器控制器根据逻辑地址空间接收存储器指令。 响应于逻辑地址空间内的不同地址的相对使用，存储器控制器以减少所使用的存储器件的数量的方式将逻辑地址空间映射到物理存储器。 然后将其它存储器件设置为降低功率模式。 在另一个实施例中，操作系统维护指示未被分配的物理存储器的部分的空闲页面列表。 操作系统按组定期对该列表进行排序，其中每个组对应于一组或多个存储器件。 这些组按照从接受最重用法的用户顺序排列到接收最轻的用户。 分配内存时，从排序的页面列表中分配内存，以便从已经接收到最高使用率的那些内存设备中优先分配内存。