Invention Grant
- Patent Title: Effective gate length circuit modeling based on concurrent length and mobility analysis
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Application No.: US13187201Application Date: 2011-07-20
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Publication No.: US08136079B2Publication Date: 2012-03-13
- Inventor: Kanak B. Agarwal , Vivek Joshi
- Applicant: Kanak B. Agarwal , Vivek Joshi
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Garg Law Firm, PLLC
- Agent Rakesh Garg; Libby Z. Toub
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50 ; G06F11/22

Abstract:
Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current.
Public/Granted literature
- US20110283251A1 Effective Gate Length Circuit Modeling Based On Concurrent Length And Mobility Analysis Public/Granted day:2011-11-17
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