Abstract:
The present invention provides methods for quantitating one or more biomolecules in a sample using IR based techniques, sample holder devices for use in such methods as well as methods for manufacturing such sample holder devices.
Abstract:
A domino circuit may be provided with additional keeper transistors that are selectively activated when one of the input transistors in a logic structure has a low or inactive signal applied to it during the evaluation stage. Thus, the potential of the output node of the domino circuit may be maintained, improving the soft error rate.
Abstract:
The present invention provides methods for quantitating one or more biomolecules in a sample using IR based techniques, sample holder devices for use in such methods as well as methods for manufacturing such sample holder devices.
Abstract:
Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current.
Abstract:
A method that includes steps for determining an optimum splitting variable and dividing a programmable logic array (PLA) into a first sub-PLA and a second sub-PLA based on the splitting variable is presented. The method also provides for gating logic to be applied to the first sub-PLA and the second sub-PLA. Power consumption is then controlled in the first sub-PLA and the second sub-PLA so only one of the first sub-PLA and the second sub-PLA contributes to power consumption. In another embodiment, a PLA be recursively divided into a plurality of sub-PLAs.
Abstract:
The rate-based scheduling for a network application is used to control the bandwidth available to a flow while scheduling the transmission of the flow. The rate-based scheduling uses rate credits to represent the amount of data a flow is permitted to transmit and only permits a flow to transmit if the flow has rate credit available. A flow is permitted to transmit only if the peak packet rate for the scheduler has not been exceeded.
Abstract:
A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.
Abstract:
A memory is divided into a number of partitions. The partitions are grouped into a first group of partitions and a second group of partitions. When required by a port, a partition is assigned to the port from a pool of un-assigned partitions. The pool of un-assigned partitions comprises of un-assigned partitions from the first group of partitions and un-assigned partitions from the second group of partitions. The un-assigned partitions from the first group of partitions are assigned to the port until a first threshold is reached. The un-assigned partitions from the second group of partitions are assigned to the port after the first threshold is reached. A second threshold is used to limit a total number of partitions assigned to the port.
Abstract:
A mechanism is provided for reducing the power consumption of a register file by disabling unused register file read ports. A selected entry of the register file is hardwired to zero and the address of the selected entry is driven to the address decoder of the register file in response to a power-down condition. The power-down condition occurs when, for example, no valid address is driven to the read port, i.e. the read port is unused. For one embodiment of the invention, the selected entry is the zeroth entry of the register file, and the address lines are grounded when an address valid bit associated with the read port is not asserted.
Abstract:
A method and apparatus for a CMOS inverter is provided for incrementing a first number by a one, three, or multiple of two. The incrementing unit includes an extract/restore unit for extracting a number of least significant bits from the first number, thereby producing a second number. The number of least significant bits extracted is determined by the incrementing value. The incrementing unit further includes an adjusting unit for adding an adjusting value to the least significant bits extracted from the first number, thereby producing an adjusted least significant bits. The incrementing unit further includes an incrementor block for receiving the second number and incrementing the second number, thereby producing a fourth number. The the extract/restore unit further for restoring the adjusted least significant bits to the fourth number, thereby producing a final result.