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    Data driven keeper for a domino circuit
    2.
    发明授权
    Data driven keeper for a domino circuit 有权
    数据驱动的守护者为多米诺骨牌电路

    公开(公告)号：US06559680B2

    公开(公告)日：2003-05-06

    申请号：US09448250

    申请日：1999-11-24

    Applicant: Bharat Bhushan ,  Vivek Joshi

    Inventor： Bharat Bhushan ,  Vivek Joshi

    IPC: H03K19096

    CPC classification number: H03K19/0963

    Abstract: A domino circuit may be provided with additional keeper transistors that are selectively activated when one of the input transistors in a logic structure has a low or inactive signal applied to it during the evaluation stage. Thus, the potential of the output node of the domino circuit may be maintained, improving the soft error rate.

    Abstract translation: 多米诺骨牌电路可以设置有附加的保持器晶体管，当逻辑结构中的一个输入晶体管在评估阶段期间施加到其上时，其被选择性地被激活。 因此，可以维持多米诺骨电路的输出节点的电位，提高软错误率。

    EFFECTIVE GATE LENGTH CIRCUIT MODELING BASED ON CONCURRENT LENGTH AND MOBILITY ANALYSIS
    4.
    发明申请
    EFFECTIVE GATE LENGTH CIRCUIT MODELING BASED ON CONCURRENT LENGTH AND MOBILITY ANALYSIS 有权
    基于同期长度和移动性分析的有效门限长度电路建模

    公开(公告)号：US20100257493A1

    公开(公告)日：2010-10-07

    申请号：US12416222

    申请日：2009-04-01

    Applicant: Kanak B. Agarwal ,  Vivek Joshi

    Inventor： Kanak B. Agarwal ,  Vivek Joshi

    IPC: G06F17/50

    CPC classification number: G06F17/5036

    Abstract: Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current.

    Abstract translation: 公开了一种用于确定金属氧化物半导体（MOS）门功能限制的计算机实现方法和计算机程序产品。 模拟器获得MOS门的多个片，每个片包括至少一个参数，该参数包括片栅宽度和片栅长度。 模拟器基于切片的切片门限长度确定每个切片的电流，以形成每个切片的基于长度的电流。 模拟器通过对每个切片的基于长度的电流求和来确定MOS栅极的基于长度的电流。 模拟器计算每个切片的应力分布。 模拟器基于每个切片的应力分布来确定每个切片的切片载波移动性。 模拟器基于每个切片载波移动性确定每个切片的基于载波移动性的电流。 模拟器基于每个切片的基于载波移动性的电流来确定MOS栅极的载流子迁移率。 模拟器基于长度电流确定MOS栅极的有效长度。

    Method to reduce the power consumption of large PLAs by clock gating guided by recursive shannon decomposition of the and-plane
    5.
    发明授权
    Method to reduce the power consumption of large PLAs by clock gating guided by recursive shannon decomposition of the and-plane 失效
    通过由平面的递归香农分解引导的时钟门控来降低大型PLA的功耗的方法

    公开(公告)号：US07065732B1

    公开(公告)日：2006-06-20

    申请号：US09678175

    申请日：2000-09-28

    Applicant: Victor Konrad ,  Vivek Joshi

    Inventor： Victor Konrad ,  Vivek Joshi

    IPC: G06F17/50 ,  H03K17/693 ,  H03K19/177

    CPC classification number: G06F17/5054

    Abstract: A method that includes steps for determining an optimum splitting variable and dividing a programmable logic array (PLA) into a first sub-PLA and a second sub-PLA based on the splitting variable is presented. The method also provides for gating logic to be applied to the first sub-PLA and the second sub-PLA. Power consumption is then controlled in the first sub-PLA and the second sub-PLA so only one of the first sub-PLA and the second sub-PLA contributes to power consumption. In another embodiment, a PLA be recursively divided into a plurality of sub-PLAs.

    Abstract translation: 提出了一种方法，其包括用于确定最佳分割变量并基于分割变量将可编程逻辑阵列（PLA）划分为第一子PLA和第二子PLA的步骤。 该方法还提供了门控逻辑应用于第一辅助解决方案和第二辅助解决方案。 然后在第一sub-PLA和第二sub-PLA中控制功率消耗，所以第一sub-PLA和第二sub-PLA中只有一个有助于功耗。 在另一实施例中，PLA被递归地分成多个子PLA。

    Method and apparatus for low power domino decoding
    7.
    发明授权
    Method and apparatus for low power domino decoding 有权
    低功耗多米诺解码的方法和装置

    公开(公告)号：US06593776B2

    公开(公告)日：2003-07-15

    申请号：US09922434

    申请日：2001-08-03

    Applicant: Sudarshan Kumar ,  Gaurav Mehta ,  Vivek Joshi

    Inventor： Sudarshan Kumar ,  Gaurav Mehta ,  Vivek Joshi

    IPC: H03K1994

    CPC classification number: G11C8/10

    Abstract: A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.

    Abstract translation: 解码器包括多个解码门，每个解码门提供解码输出信号的一位。 至少两个解码门共享晶体管。 根据一个方面，多个解码门中的每一个是偏斜门。

    Low power register file
    9.
    发明授权
    Low power register file 有权
    低功率寄存器文件

    公开(公告)号：US06564331B1

    公开(公告)日：2003-05-13

    申请号：US09405825

    申请日：1999-09-24

    Applicant: Vivek Joshi

    Inventor： Vivek Joshi

    IPC: G06F132

    CPC classification number: G06F9/30141 ,  G06F1/3228

    Abstract: A mechanism is provided for reducing the power consumption of a register file by disabling unused register file read ports. A selected entry of the register file is hardwired to zero and the address of the selected entry is driven to the address decoder of the register file in response to a power-down condition. The power-down condition occurs when, for example, no valid address is driven to the read port, i.e. the read port is unused. For one embodiment of the invention, the selected entry is the zeroth entry of the register file, and the address lines are grounded when an address valid bit associated with the read port is not asserted.

    Abstract translation: 提供了一种通过禁用未使用的寄存器文件读取端口来减少寄存器文件的功耗的机制。 寄存器文件的选定条目硬连线为零，并且所选条目的地址响应于掉电状态被驱动到寄存器堆的地址解码器。 当例如没有有效地址被驱动到读端口，即读端口未使用时，发生掉电状况。 对于本发明的一个实施例，所选择的条目是寄存器文件的第零条目，并且当与读取端口相关联的地址有效位未被确认时，地址线接地。

    CMOS sum select incrementor
    10.
    发明授权
    CMOS sum select incrementor 失效
    CMOS和选择增量器

    公开(公告)号：US5889693A

    公开(公告)日：1999-03-30

    申请号：US851220

    申请日：1997-05-05

    Applicant: Vivek Joshi ,  Sudarshan Kumar

    Inventor： Vivek Joshi ,  Sudarshan Kumar

    IPC: G06F7/50 ,  G06F7/505 ,  G06K7/50

    CPC classification number: G06F7/5055 ,  G06F7/507

    Abstract: A method and apparatus for a CMOS inverter is provided for incrementing a first number by a one, three, or multiple of two. The incrementing unit includes an extract/restore unit for extracting a number of least significant bits from the first number, thereby producing a second number. The number of least significant bits extracted is determined by the incrementing value. The incrementing unit further includes an adjusting unit for adding an adjusting value to the least significant bits extracted from the first number, thereby producing an adjusted least significant bits. The incrementing unit further includes an incrementor block for receiving the second number and incrementing the second number, thereby producing a fourth number. The the extract/restore unit further for restoring the adjusted least significant bits to the fourth number, thereby producing a final result.

    Abstract translation: 提供了一种CMOS反相器的方法和装置，用于将第一数量增加一个，三个或两个倍数。 递增单元包括用于从第一数量提取多个最低有效位的提取/恢复单元，从而产生第二数量。 提取的最低有效位的数量由递增值确定。 增量单元还包括调整单元，用于将调整值与从第一数量提取的最低有效位相加，从而产生经调整的最低有效位。 递增单元还包括用于接收第二数量并递增第二数量的增量块，从而产生第四数。 所述提取/还原单元还用于将经调整的最低有效位恢复到第四数，从而产生最终结果。

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